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responder3
基于VHDL的多路抢答器,用LCD12864进行显示(Multiplex answering device based on VHDL is displayed with LCD12864)
- 2019-06-17 15:29:31下载
- 积分:1
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电子密码锁
电子密码锁-Electronic Code Lock
- 2022-09-25 17:35:03下载
- 积分:1
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myfir
verilog编写的16阶升余弦滤波器 采用直接型结构实现 对方波进行滤波 输出波形 含testbench文件(order raised cosine filter verilog written 16 direct-type structure to achieve the other wave filtering the output waveform containing testbench file)
- 2020-10-05 16:47:44下载
- 积分:1
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RLC Test
说明: RLC Test程序,一个电子竞赛的题目。里面有详尽的源代码。(RLC Test procedures, an electronic race issue. There are detailed source code.)
- 2005-09-04 20:58:18下载
- 积分:1
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dazhuankuai
基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)
- 2013-11-26 09:40:37下载
- 积分:1
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USB 1.1 IP
USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
- 2022-05-24 18:47:17下载
- 积分:1
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Kay_algorithm
QPSK调制的载波频偏估计,是一个可以调用的函数。接收端进行了一系列的处理。经典的Kay法(QPSK-carrier frequence offset estimation_ kay )
- 2013-03-18 14:36:29下载
- 积分:1
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m_ca7
verilog编写的基于CA算法的m序列发生器,其中验证了多种CA系数来实现m序列。(CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.)
- 2011-10-26 14:33:59下载
- 积分:1
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8位大小比较器
说明: 8位大小比较器的VHDL源代码,Magnitude Comparator
VHDL description of a 4-bit magnitude comparator with expansion inputs(eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion)
- 2005-10-28 22:35:12下载
- 积分:1
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frequency divider
说明: FPGA对系统50M时钟进行分频。FPGA最基本功能基础(FPGA Verilog program, key detection, program jitter elimination, jitter elimination, delay detection keys)
- 2019-04-27 23:35:12下载
- 积分:1