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FPGA60进制数码管显示VHDL代码
FPGA设计中的60进制计数器,通过2个七段数码管系那是出来。代码简单易懂,仿真通过,而且在FPGA开发板上加载显示成功。很有用的入门代码。
- 2022-07-12 13:55:48下载
- 积分:1
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capture-using-SCCB-and-FPGA
利用SCCB和FPGA实现视频采集的论文,对相关开发人员具有很强的参考价值!
(FPGA implementation using the SCCB and video collection of the papers, the relevant developer has a strong reference value !
)
- 2013-09-29 15:37:52下载
- 积分:1
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stopwatch
数字秒表的VHDL代码。当设计文件加载到目标器件后,设计的数字秒表从00-00-00开始计秒。,直到按下停止按键(按键开关S2)。数码管停止计秒。按下开始按键(按键开关S1),数码管继续进行计秒。按下复位按键(核心板上复位键)秒表从00-00-00重新开始计秒。(The VHDL code for digital stopwatch. When the design document loaded into the target device, the designed digital stopwatch count the seconds from the 00-00-00. Until you press stop key (key switch S2). Nixie tube stop count seconds. Press the start button (key switch S1), the digital control continue to count seconds. Press the reset button (core panel reset button) to restart the stopwatch count seconds from the 00-00-00.)
- 2010-03-02 17:17:58下载
- 积分:1
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cic
cic设计 verilog verilog(cic verilog design verilog)
- 2012-10-23 20:13:52下载
- 积分:1
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scramble
基于VHDL实现加扰器解扰器的设计,与仿真。(VHDL-based scrambler descrambler design and simulation.)
- 2013-01-11 20:15:54下载
- 积分:1
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Three-phase-power
利用FPGA,产生三相SPWM波,与后继硬件电路配合,形成三相电源。高效,实用。(Using FPGA, produce three-phase SPWM wave, with subsequent hardware circuit with the formation of three-phase power. Efficient and practical.)
- 2021-04-06 23:49:02下载
- 积分:1
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11-07-11
AD9910实现脉冲内线性调频信号,仅供参考(AD9910 to achieve linear FM pulse signal, for reference only)
- 2013-09-16 10:52:00下载
- 积分:1
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mp3codec
it is used to compile codec
- 2009-03-04 17:00:53下载
- 积分:1
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freeDev数字应用开发板中的七段数码管的IP核的verilog实现
freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
- 2022-01-31 19:57:07下载
- 积分:1
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(1)距离算法研究和设计;
(2)采用FPGA/CPLD实现。
(1)距离算法研究和设计;
(2)采用FPGA/CPLD实现。
-(1) distance algorithm and design (2) using FPGA/CPLD implementation.
- 2022-08-13 17:17:05下载
- 积分:1