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4BITMUIT
利用LPM_MUIT宏模块设计一个四位数据乘法器(Use LPM_MUIT macro module design a four data Multiplier)
- 2013-09-05 10:06:52下载
- 积分：1
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sph-original-codes
SPH的原始代码，希望可以帮到大家啊关于模拟poiseuille的(simulate poiseuille fuild)
- 2020-10-22 10:27:23下载
- 积分：1
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FPGA 出租计费器
本代码绝对真实可靠，原用于长沙理工大学EDA课程设计之出租车计费器。本代码在要求的基础上添加显示时速和报警功能。希望此代码对有此需求的同学有所帮助！
- 2022-01-25 20:43:32下载
- 积分：1
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fenpin
这是一个二进制的最简单分频器，是一个简短的fpga代码，用verilog书写(This is the most simple of a binary frequency divider, the fpga is a short code, written in verilog)
- 2013-11-17 15:01:30下载
- 积分：1
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作为一个简明的教程，主要宗旨是让初学者快速地了解FPGA/SOPC（可编程片上系统）开发的流程。...
作为一个简明的教程，主要宗旨是让初学者快速地了解FPGA/SOPC（可编程片上系统）开发的流程。-As a simple tutorial, the main purpose is to enable beginners to understand Express FPGA/SOPC (system on programmable chip) development process.
- 2022-02-05 10:08:14下载
- 积分：1
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10进制计数器的VHDL描述必须实验
10进制计数器，VHDL描述的，实验必备-10 hexadecimal counters, VHDL description of the experiment must
- 2022-03-17 18:09:21下载
- 积分：1
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verilog HDL语言编写的键盘扫描程序，考虑以确定关键的博…
Verilog HDL编写的键盘扫描程序，考虑了判断按键弹起的问题。程序按一定的频率用低电平循环扫描行线，同时检测列线的状态，一旦判断有一列为低则表示有键被按下，停止扫描并保持当前行线的状态，再读取列线的状态从而得到当前按键的键码；等待按键弹起：检测到各列线都变成高点平后，重新开始扫描过程，等待下一次按键。-Written in Verilog HDL keyboard scanner, taking into account to determine key bounce problem. Program according to a certain frequency of scan lines with low-level circulation lines, while testing out the state line, once the judge has said there is a classified as low-key is pressed, stop the scan and to maintain the current line-line state, and then read out line state to get the current keys key codes to wait for key pop-up: To detect the lines at all out into a high level after the re-start the scanning process, waiting for the next key.
- 2022-05-07 15:33:47下载
- 积分：1
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taxi
利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
- 2011-08-30 08:18:51下载
- 积分：1
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Verilog prepared using USB download cable program realize USB protocol and JTAG...
用verilog编写的USB下载线程序 实现USB协议和JTAG接口的数据转换实现状态机-Verilog prepared using USB download cable program realize USB protocol and JTAG interface to achieve data conversion state machine
- 2022-01-26 07:07:00下载
- 积分：1
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XADC
xilinx verilog FPGA驱动AD9613 数据采集DEMO程序(Xilinx Verilog FPGA drives AD9613 data acquisition DEMO program.)
- 2021-03-29 15:19:10下载
- 积分：1
