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vhdl数据通路

于 2023-03-31 发布 文件大小:7.80 kB
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用于实现fpag-cpu的数据通路源代码。用vhdl编写,包括内存,寄存器组,和alu(简陋的alu,仅包含加法器)三大部分通过手动微指令输入信号,可以往内存写入数据,并加载到寄存器组中,通过alu产生结果,结果保存在一个锁存器中,可以把结果写回寄存器组或者内存。本人在quartus下编写仿真通过。附件中未给出相关工程文件。

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