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modulation-and-demodulation
通过verilog语言实现各种基本信号的调制解调过程，包括2psk,qpsk,ppm(Realize the modulation and demodulation process of various basic signals through verilog language, including 2psk, qpsk, ppm)
- 2018-04-26 21:52:04下载
- 积分：1
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温度码到二进制吗的转换的ｖｅｒｉｌｏｇＨＤＬ代码。
温度码到二进制吗的转换的ｖｅｒｉｌｏｇＨＤＬ代码。-Temperature code to do the conversion of binary code verilogHDL.
- 2022-02-28 22:15:49下载
- 积分：1
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vhdl 语言代码多路复用器
multiplexerwe 的 vhdl 程序可以写也像 thisits 非常简单的代码为 beginers 了解 4： 1 多路复用器
- 2023-04-22 00:05:03下载
- 积分：1
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VHDL example, there are nearly a hundred examples, can be carried out in quartur...
VHDL实例,有近百个实例,都是可以在quarturs 上进行仿真的,大部分都可以通过,对初学者是一非常不错的-VHDL example, there are nearly a hundred examples, can be carried out in quarturs simulation, most of them can pass, for beginners is a very good
- 2022-04-16 23:40:20下载
- 积分：1
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I2S_2
that file is different I2S example
- 2014-11-27 06:39:52下载
- 积分：1
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代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心...
代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping
- 2022-04-13 03:11:13下载
- 积分：1
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eth_send
清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。(Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.)
- 2010-09-26 14:43:28下载
- 积分：1
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本代码实现了全加器功能，适合初学者学习
本代码实现了全加器的功能，可供初学者学习-This code implements a full adder functions, for beginners to learn
- 2022-03-09 20:15:10下载
- 积分：1
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这是一个数字时钟数字逻辑电路，整个工程包上传…
这是一个数字时钟的数字逻辑电路，整个工程打包上传，时钟可以计时、校时、整点报时、定时闹钟。使用电路图实现的。在quatarsII里面仿真的并且下载到DE2板上运行过。-This is a digital clock digital logic circuits, the whole project package upload, the clock could be time, school hours, the whole point timekeeping, timing alarm clock. The use of circuit implementation. The quatarsII inside the simulation, and downloaded to the DE2 board to run-off.
- 2022-08-06 10:22:24下载
- 积分：1
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XC3S700_UART_Test
红色飓风3S700AN开发板UART测试例程(Red Hurricane 3S700AN development board UART test code)
- 2013-07-12 00:34:31下载
- 积分：1
