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VHDL
A Full adder using half adder unit in vhdl
- 2010-01-05 11:39:14下载
- 积分：1
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基于sopc ep2c5开发板的时间标记服务例程
基于sopc ep2c5开发板的时间标记服务例程-Sopc ep2c5 development board based on the time-stamping services routines
- 2022-02-26 04:39:24下载
- 积分：1
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Several Example FPGA design contest
几个fpga竞赛的设计例-Several Example FPGA design contest
- 2022-09-16 03:50:03下载
- 积分：1
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Microcomputer-Principle
该书介绍了英特尔的80x86CPU和一些串行通信芯片，以及汇编语言。(The book introduces the Intel 80x86CPU and some serial communications chip, and assembly language.)
- 2013-07-27 14:55:25下载
- 积分：1
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DE0-PWM-Led-Drive---simulation
DE0_PWM_LED_DRİ VE_Sİ MULATİ ON
- 2015-12-04 16:32:56下载
- 积分：1
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8psk
在matlab中8psk的调制和解调仿真程序(the modulation and demodulation of 8psk)
- 2013-05-02 09:54:07下载
- 积分：1
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HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
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Baseband_line_code
基于VHDL语言的基带线路码产生电路设计（毕业论文），内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
- 2010-07-03 22:38:09下载
- 积分：1
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Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核...
Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
- 2022-02-06 18:05:18下载
- 积分：1
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这是一个简单的除法器（32bit/16bit),采用移位相减法
这是一个简单的除法器（32bit/16bit),采用移位相减法-This is a simple divider (32bit/16bit), using phase shift subtraction
- 2022-07-06 17:00:38下载
- 积分：1
