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MP3-coder
In this design, it is assumed that a buffer sized as 1024x8 bits provides main data including scale factors and Huffman code bits to Huffman decoder.
Also, it is assumed that a memory with 1024x8 bits is ready for each component to write or read the output or input 576 frequency lines.(This folder contains three directories: Huffman, IMDCT and Filterbank, each of them
includes all the VHDL source codes of the component.)
- 2013-08-06 15:40:24下载
- 积分：1
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频率计，ＶＥＲＩＬＯＧ代码，含详细 中文注释．
频率计，ＶＥＲＩＬＯＧ代码，含详细 中文注释．-Cymometer, VERILOG code, containing a detailed Chinese Notes.
- 2023-05-22 17:20:02下载
- 积分：1
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VHDL 加法器
这个程序是 用于两个浮点数字加法器使用 VHDL 语言。
- 2022-02-06 15:47:18下载
- 积分：1
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vhdl 基于ADC0809 A/D转换控制器的设计实验
vhdl 基于ADC0809 A/D转换控制器的设计实验-vhdl ADC0809
- 2022-02-25 21:38:23下载
- 积分：1
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airthmatic & logic unit
airthmatic & logic unit
- 2023-02-23 08:10:03下载
- 积分：1
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一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐...
一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
- 2022-03-07 12:48:23下载
- 积分：1
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cic_compensating
CIC 补偿滤波器。采用两种方法来设计，一个是frequency sampling method。另一个是Equal Rippler Design Method。这是一个非常有用的matlab代码。(CIC compensation filter. Two ways to design a frequency sampling method. The other is an Equal Rippler Design Method. This is a very useful matlab code.)
- 2012-10-17 14:22:08下载
- 积分：1
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设计一个可以小时、分钟、12小时或24小时和秒的时间…
设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟，并具有定时与闹钟功能，能在设定的时间发出闹铃音，能非常方便地对小时、分钟和秒进行手动调节以校准时间，每逢整点，产生报时音报时。
实验平台：
1. 一台PC机；
2. MAX+PLUSII10.1。
Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
- 2022-07-22 15:10:59下载
- 积分：1
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FPGA
基于FPGA的电机控制
FPGA-basedMotorControl-FPGA-based motor control FPGA-basedMotorControl
- 2022-04-13 15:15:14下载
- 积分：1
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CPLD_DEMO_OK
可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)
- 2011-01-12 21:09:45下载
- 积分：1
