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Verilog
verilog编程语言的讲解,有电子科技大学出版(verilog programming language to explain, there is the University of Electronic Science and Technology Publishing)
- 2013-08-14 09:21:43下载
- 积分:1
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高科技的发展使芯片设计不再是半导体工业的领域,现场可编程逻辑阵列(FPGA)的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专...
高科技的发展使芯片设计不再是半导体工业的领域,现场可编程逻辑阵列(FPGA)的出现使通过软件来快速实现芯片设计成为可能。本系统是广泛面向全球的工程技术人员和大专院校学生,使您能够在最短的时间内掌握FPGA的应用与VHDL/AHDL/Verilog HDL这一电子逻辑设计利器,迅速的加入高级电子设计人才行列。-The development of high-tech chip design is no longer the field of semiconductor industry, field programmable logic arrays (FPGA) through the emergence of chip design software to quickly achieve the possible. This system is a broad global engineering and technical personnel and college students, so that you can in the shortest possible period of time to master the application of FPGA and VHDL/AHDL/Verilog HDL logic design of the electronic weapon, quickly adding advanced electronic design talent ranks.
- 2023-05-14 03:35:03下载
- 积分:1
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sample_wave
可以产生8比特的采样波形,非常不错的VHDL程序(Sampling can produce 8-bit waveform, very good VHDL program)
- 2010-10-12 20:03:07下载
- 积分:1
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DE2 VGA控制代码,de2上控制VGA
DE2 VGA控制代码,de2上控制VGA-DE2 VGA control code, de2 to control VGA
- 2022-04-17 02:33:42下载
- 积分:1
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PS2键盘控制程序实验的内容是用EDK建一个简单的系统并加入自定义的外设(一个ps2键盘控制器)
当键盘按下时会有相应的键扫描码输出显示到PC终端...
PS2键盘控制程序实验的内容是用EDK建一个简单的系统并加入自定义的外设(一个ps2键盘控制器)
当键盘按下时会有相应的键扫描码输出显示到PC终端
-PS2 keyboard to control the content of the experimental procedure is used EDK build a simple system and add custom peripherals (a ps2 keyboard controller) when the keyboard is pressed the corresponding button will scan code to the PC terminal output shows
- 2022-03-26 18:34:50下载
- 积分:1
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E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
- 2023-06-23 08:30:04下载
- 积分:1
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USB IPcoreIP核 包含文档(带说明)
USB IPcoreIP核 包含文档(带说明)-USB IPcoreIP core includes a document (with instructions)
- 2022-02-18 17:02:37下载
- 积分:1
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ANALYSIS-OF-ALL-GATES
ANALYSIS OF ALL GATESS
- 2013-11-12 13:33:55下载
- 积分:1
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performance with rayleigh
matlab bpsk with rayleigh performance expirement
- 2020-06-24 21:40:01下载
- 积分:1
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A signal can be stretched any one CLk the VHDL source code examples. See documen...
一个可以把信号拉长任意个CLk的VHDL源码例子。详见说明文档-A signal can be stretched any one CLk the VHDL source code examples. See documentation
- 2022-03-24 02:54:32下载
- 积分:1