-
crc24_d1
CRC24的verilog实现,LTE的3GPP 36.212里面对应的CRC添加(the implementation of CRC24 in verilog)
- 2018-06-06 14:16:10下载
- 积分:1
-
SPI接口代码
对SPI接口的verilog编程,SPI is a simple interface that allows one chip to communicate with one or more other chips.
- 2022-04-16 11:02:29下载
- 积分:1
-
LCD1602
通过编写verilog语言完成数据的在液晶LCD1602显示(By writing verilog language to complete the data displayed on the LCD LCD1602)
- 2013-08-04 13:12:05下载
- 积分:1
-
fpga_sdram_inst
nios学习资料,fpga调用外部sdram实例,值得初学者下载。(nios learning materials, fpga call external sdram instance, it is worth beginners to download.)
- 2013-08-24 22:26:31下载
- 积分:1
-
基于AHB总线的DMAC系统
传输特点
1.传输size为字传输。(总线的字长为32位,每次传输32位数)
2.16拍的增量突发传输。
3.支持2个AHB接口,一个用来配置DMA内部寄存器,
4.采用独占总线的方法,当DMA占用总线时,CPU停止一切活动。
5.支持异步复位。
6.本次设计的MDA每次最多传输256个数据,每次总线传输最多传16个数据,
- 2022-02-04 17:46:50下载
- 积分:1
-
gg
说明: FPGA实现基带成型滤波器,升余弦滚降系数,多进制调制(FPGA)
- 2010-12-20 17:55:18下载
- 积分:1
-
adder_array
adder_array的设计。加法器阵列设计,顶层模块,四步流水,21位(adder_array the design. The adder array design, top-level module, four-step pipeline, 21)
- 2013-04-17 00:19:05下载
- 积分:1
-
PA3_E_FROM_AN
actel flash rom使用 actel flash rom使用(actel flash rom actel flash rom)
- 2013-05-07 14:42:44下载
- 积分:1
-
leadingzero
使用并行结构对32位数据进行前导零检测,使用Verilog编程(Use parallel structure to the 32-bit data, leading zero detection, using Verilog Programming)
- 2010-05-12 10:48:36下载
- 积分:1
-
mimo_dectection
mimo检测算法的FPGA实现,包括最小迫零检测算法和ML检测算法,已在ISE上仿真通过
(mimo detection algorithm for FPGA implementation, including the smallest zero forcing detection algorithm and ML detection algorithm has been simulated by ISE on)
- 2021-02-15 12:09:48下载
- 积分:1