-
FPGA正弦信号发生器
基于verilog hdl编写的FPGA正弦信号发生器,已测试。(FPGA sine signal generator)
- 2020-11-10 10:59:46下载
- 积分:1
-
color_bar
彩条产生程序。。。。720p需添加74.25M时钟(colorbar generation. need 74.25mhz clock if 720p gen)
- 2020-06-22 06:20:01下载
- 积分:1
-
DDS signal generator, can produce a variety of waveforms, are mysterious wave, t...
DDS信号发生器,能产生多种波形,正玄波,三角波,方波,频率可调,相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable
- 2022-11-28 01:05:04下载
- 积分:1
-
moore-FSM
该程序描述并且模拟和实现了了一个摩尔有限状态机的功能和作用(The program describes the simulation and the function and role of a mole finite state machine)
- 2013-05-10 10:27:09下载
- 积分:1
-
Риторика_Зачетная работа
说明: access must be conf urr arr
- 2019-05-29 20:23:53下载
- 积分:1
-
filter
说明: A low pass filter module based on FPGA, easy to transplant
- 2020-05-04 10:21:42下载
- 积分:1
-
max_plus开发的 有max_plus就可以直接运行的交通灯制作 用vhdl语言编写的...
max_plus开发的 有max_plus就可以直接运行的交通灯制作 用vhdl语言编写的-max_plus development of max_plus can direct the operation of traffic lights produced by VHDL language
- 2022-07-18 11:58:04下载
- 积分:1
-
i2s_input
基于FPGA的i2s接口输入模块设计,其中有原理图和verilog源码,可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)
- 2020-12-14 16:49:14下载
- 积分:1
-
用FPGA实现的模糊控制器 部分用VHDL编写的源程序
用FPGA实现的模糊控制器 部分用VHDL编写的源程序-Using FPGA to achieve some of the fuzzy controller using VHDL source code prepared
- 2022-03-26 02:28:39下载
- 积分:1
-
USB_Serial1
实现basys3板子的串口通信,内容非常纤细,还带有数码管显示(Realization of serial communication of basys3 board)
- 2021-03-26 17:19:13下载
- 积分:1