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pingball
说明： 这是一个带声音的弹球小游戏，通过VGA口显示，通过扩展口JA的 pin4和 pin GND输出声音， BTN3 BTN2 控制挡板左右移动，弹球和挡板都自带动画效果(This is a band sound pinball game, through the VGA port shows that through the expansion of the mouth of the JA and pin4 output pin GND voice, BTN3 BTN2 control baffle around Mobile, pinball and baffle all bring their own animation effects)
- 2008-11-09 00:34:49下载
- 积分：1
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bhas
this is a vhdl program...
- 2013-08-17 23:30:56下载
- 积分：1
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piso8_ok_bingchuanzhuanhuan
本程序是用vhdl开发的实现并串转换功能的程序。(This procedure is developed using VHDL implementation and string conversion function of the program.)
- 2017-06-07 15:50:38下载
- 积分：1
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TugasUAS_AuditTI_1504505017_Reguler
说明： ertyguhijop[lkjhvbn hiouopi][[poiuy
- 2019-02-05 09:18:23下载
- 积分：1
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USB1.1 IP核心控制设备，用硬件描述语言…
usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
- 2022-01-30 21:54:55下载
- 积分：1
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ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示...
ALTERA NIOS处理器，用VHDL在QUARTUS下编写，用NIOS SHELL调试通过，实验LCD液晶显示-Altera NIOS processor, using VHDL in QUARTUS prepared with NIOS SHELL debug through experimental LCD
- 2022-03-20 10:53:06下载
- 积分：1
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托马斯的教科书Verilog。Verilog的托马斯在该领域的著名…
Thomas课本中的verilog例子。Thomas的verilog在可编程期间领域很有名-Thomas textbook example of verilog. Verilog Thomas in the field during the famous programmable
- 2022-03-07 05:06:40下载
- 积分：1
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大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持...
大名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-famous Synopsys Core 8051IP the VHDL language, can be supported keilC51
- 2022-11-25 02:20:03下载
- 积分：1
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基于FPGA的信号发生器20140506
说明： 基于FPGA的芯片信号发生器，利用Verilog语言实现信号发生器的各个模块单元，
实现的要求：正弦波、三角波、方波等；(Based on FPGA chip signal generator, using Verilog language to realize each module unit of the signal generator, Requirements: sine wave, triangle wave, square wave, etc;)
- 2019-12-30 11:48:26下载
- 积分：1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分：1
