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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分:1
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AES-on-FPGA
AES算法在FPGA上的实现,对AES算法所用的器件资源进行了总结(AES on FPGA the Fastest to the Smallest)
- 2014-12-31 10:06:46下载
- 积分:1
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vhdl_ders_1_temel_bilgiler
VHTL PROGRAMMING COURSE
- 2009-07-11 22:24:59下载
- 积分:1
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ofdm
这是OFDM调制matlab的程序,中间详细描述了调制的过程,希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)
- 2013-09-26 16:20:42下载
- 积分:1
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pl_read_write_ps_ddr
说明: PL 和 PS 的高效交互是 zynq 7000 soc 开发的重中之重,常常需要将 PL 端的大量数据实时送到 PS 端处理,或者将 PS 端处理结果实时送到 PL 端处理,但是各种协议非常麻烦,灵活性也比较差,直接通过 AXI 总线来读写 PS 端 ddr 的数据,这里面涉及到 AXI4 协议,vivado 的 FPGA 调试等。(The efficient interaction between PL and PS is the top priority of zynq 7000 SoC development. We often need to send a large amount of data from PL to PS for real-time processing, or send the processing results from PS to pl for real-time processing. In general, we will think of using DMA for processing, but various protocols are very troublesome and the flexibility is poor. This course explains how to use Axi directly Bus to read and write DDR data of PS terminal, which involves axi4 protocol, FPGA debugging of vivado, etc.)
- 2021-01-22 17:46:44下载
- 积分:1
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- 2022-01-25 14:18:53下载
- 积分:1
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IIC slave controller source code
IIC slave controller source code
- 2022-02-15 09:45:19下载
- 积分:1
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FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用...
FPGA VERILOG 用DCFIFO实现 跨时钟域的数据传输,已验证,直接可用-FPGA VERILOG using DCFIFO realize cross-clock domain data transfer, has been verified, directly available
- 2022-04-17 14:15:55下载
- 积分:1
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波形发生器,带TESTBENCH,
多平台
波形发生器,带TESTBENCH,
多平台
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn
-waveform generator, with TESTBENCH. Multi-platform-- the design makes use of the new shift opera tors available in the VHDL-93 std-- this design passes the Synplify synthesis check-- downloa d from : www.fpga.com.cn
- 2023-05-18 16:15:03下载
- 积分:1
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多功能信号发生器
采用quartusⅡ仿真软件实现多功能信号发生器的FPGA设计,当输入端有时钟信号输入时,各个信号发生器模块独立运行,独立存在,发出各种信号,这些信号作为数据选择器的输入信号,在数据选择器的作用下,波形切换到相应的模块输出,将通过示波器显示出相应的波形图。
- 2023-04-09 20:10:34下载
- 积分:1