登录
首页 » VHDL » 数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法...

数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法...

于 2023-04-20 发布 文件大小:32.86 kB
0 88
下载积分: 2 下载次数: 1

代码说明:

数控分频器的设计数控分频器的功能就是当在输入端给定不同输入数据时,将对输入的时钟信号有不同的分频比,数控分频器就是用计数值可并行预置的加法计数器设计完成的,方法是将计数溢出位与预置数加载输入信号相接即可。-NC NC divider divider design of its function is when the input given different input data, input the clock signal will have different sub-frequency ratio, NC prescaler value can be used include parallel preset counter adder design is completed, the method is to count the number of overflow bit with preset load to the input signal phase.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • FFT
    FFT with fix point 2*N
    2013-10-06 15:38:38下载
    积分:1
  • 电梯的vhdl设计,6层楼含开关门,警报,内部请求,外部请求
    电梯的vhdl设计,6层楼含开关门,警报,内部请求,外部请求-Vhdl elevator design, six floors with switch doors, alarm, internal requests and external requests
    2022-06-27 17:04:01下载
    积分:1
  • air
    空调温控电路有限状态自动机, 有TEMP_HIGH和TEMP_LOW 分别与传感器相连用语检测室内温度.-air-conditioning temperature control circuit finite state automaton, and TEMP_LOW TEMP_HIGH with sensors connected to the indoor temperature detection terminology.
    2022-04-25 13:00:13下载
    积分:1
  • GAL
    有关gal器件的编程入门,以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)
    2013-07-09 22:50:01下载
    积分:1
  • Acoustic-Fingerprinting-master
    acousting fingerprint enhancement
    2019-06-03 21:23:50下载
    积分:1
  • asynchronous-fifo
    同步fifo的调用程序,调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
    2013-08-23 21:58:56下载
    积分:1
  • 基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。
    基于FPGA的门级逻辑实现快速乘法运算的verilog源程序。-FPGA-based gate-level logic implementation of rapid multiplication of the verilog source.
    2022-02-21 06:32:58下载
    积分:1
  • usbhostslave
    说明:  USB主机和设备的verilog代码,实现了USB1.1协议规范的要求(USB host and equipment Verilog code to achieve the USB 1.1 protocol specification requirements)
    2005-09-13 11:34:09下载
    积分:1
  • 二进制神经网络(BNN)bnn-fpga-master
    说明:  bnn-fpga是FPGA上CIFAR-10的二进制神经网络(BNN)加速器的开源实现。 加速器针对低功耗嵌入式现场可编程SoC,并在Zedboard上进行了测试。 在编写CIFAR-10测试集中的10000张图像时,错误率是11.19%。(bnn-fpga is an open-source implementation of a binarized neural network (BNN) accelerator for CIFAR-10 on FPGA. The architecture and training of the BNN is proposed by Courbarieaux et al. and open-source Python code is available. Our accelerator targets low-power embedded field-programmable SoCs and was tested on a Zedboard. At time of writing the error rate on the 10000 images in the CIFAR-10 test set is 11.19%.)
    2020-07-27 07:02:34下载
    积分:1
  • SASX
    Use of Kalman and EKF on two-phase permanent magnet synchronous motor of the state estimate CDCDCDCDCCC
    2020-06-24 11:40:02下载
    积分:1
  • 696518资源总数
  • 105547会员总数
  • 4今日下载