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我用过的verilog hdl写的SDRAM core源程序,经过测试应用
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altera嵌入式设计大赛文章,车载cots设计实现
altera嵌入式设计大赛文章,车载cots设计实现-Embedded Design Contest altera article, cots Car Design
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超大规模集成电路的VHDL基本编码…………
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1
说明: 一个解决除法溢出的例子,可以学习到很多,注释很详细(A solution to the division overflow example, you can learn a lot, very detailed notes)
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I121-v1.10
Implementation of Serial Infrared decoder for low-speed IrDA communications.
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国外经典verilog代码,很适合初学者,其中的有些概念对老手也可以考虑下...
国外经典verilog代码,很适合初学者,其中的有些概念对老手也可以考虑下-Foreign classic Verilog code, it is suitable for beginners, of which some of the concept of a veteran may also want to consider under the
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DDS signal generator, can produce a variety of waveforms, are mysterious wave, t...
DDS信号发生器,能产生多种波形,正玄波,三角波,方波,频率可调,相位可调-DDS signal generator, can produce a variety of waveforms, are mysterious wave, triangle wave, square wave, frequency tunable, phase adjustable
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基于fpga的正弦波发生器设计,有一定的参考价值,写的比较详细...
基于fpga的正弦波发生器设计,有一定的参考价值,写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
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Verilog代码支持IO中断的CPU实现
Verilog代码,支持IO,中断的cpu实现。(Verilog code, support IO, interrupt cpu implementation.)
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TugasUAS_AuditTI_1504505017_Reguler
说明: ertyguhijop[lkjhvbn hiouopi][[poiuy
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