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data_swith
verilog 代码实现串并转换，有延迟(Verilog code and string conversion, delay)
- 2011-07-31 23:58:17下载
- 积分：1
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fifo_rs232
从FIFO到到RS232的实现，用于接收和缓存数据(TripAdvisor RS232 FIFO implementation for receiving data and cache)
- 2016-08-26 13:57:23下载
- 积分：1
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memristor
忆阻器的SPICE建模模型说明及仿真结果说明(Memristor SPICE modeling and simulation results show that the model describes)
- 2020-11-29 17:09:31下载
- 积分：1
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jjj
实现了四bit计数器的功能，使用的是VHDL语言描述(Four-bit counter, using the VHDL language description)
- 2012-12-20 10:53:46下载
- 积分：1
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imply logic
说明： 由忆阻器机制设计蕴含逻辑，内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分：1
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TLC7528
fpga驱动TLC7528程序，相当好用，绝对能用(FPGA PROGRAM OF TLC7528)
- 2011-08-17 15:19:03下载
- 积分：1
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ahb2wishbone_latest.tar
AHB to Wishbone memory interface VHDL source code
- 2013-01-11 11:17:03下载
- 积分：1
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夏宇闻-Verilog数字逻辑设计教程
说明： 引入了Verilog HDL硬件描述语言介绍了信号处理与硬线逻辑设计的关系，以及有关的基本概念。(In this paper, Verilog HDL hardware description language is introduced to introduce the relationship between signal processing and hardware logic design, as well as the related basic concepts.)
- 2019-10-28 13:11:12下载
- 积分：1
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USART
基于USART的ARM与FPGA通信实验(Based on the ARM and FPGA communication experiment of USART
)
- 2017-04-15 16:58:30下载
- 积分：1
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016_versat_updown_counter
说明： Verilog实现的加减法功能计数器，通过独立的自增自减信号控制计数器进行自增计数和自减计数(Function counter of addition and subtraction implemented by Verilog)
- 2019-11-27 23:16:27下载
- 积分：1
