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ComunicationRealizationBetweenFPGAandSerialInterfa
说明: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议,给出了发送模块的vhdl源代码。
(杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.)
- 2008-11-18 15:41:34下载
- 积分:1
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VHDL的基本程序,可以用来驱动键盘,功能强大,虽然和基础
VHDL的基本程序,可以用来驱动键盘,功能强大,虽然和基础-VHDL
- 2022-05-24 06:27:35下载
- 积分:1
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C51 verilog 源代码,可以在逻辑中实现51单片机功能
C51 verilog 源代码,可以在逻辑中实现51单片机功能-C51 verilog
- 2022-08-18 06:28:41下载
- 积分:1
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bin2deci
程序来自《现代通信系统-使用matlab》英文版
已经调通!并加上了注释。
希望对大家有帮助4(fpga)
- 2009-04-02 21:16:26下载
- 积分:1
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DDS
FPGA实现DDS波形发生器,多种信号的产生,(FPGA realization of DDS waveform generator to produce a variety of signals,)
- 2014-07-20 14:31:22下载
- 积分:1
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等精度测频率
说明: 利用stm32F407实现的等精度测频,可以精确测量频率,误差很小(The equal precision frequency measurement realized by stm32F407 can accurately measure frequency with little error.)
- 2020-06-19 13:00:02下载
- 积分:1
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FPGA-Labview
Design FPGA in Labview
- 2015-05-27 23:39:27下载
- 积分:1
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基于FPGA控制的DDS波形发生器
基于FPGA控制的DDS波形发生器,可在Cyclone IV系列板子上使用,已经过仿真验证(Based FPGA control DDS waveform generator in Cyclone IV series board on use, has been simulation)
- 2017-03-17 11:08:39下载
- 积分:1
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7 digital display decoder design 7 Digital is pure combinational circuits, usual...
7段数码显示译码器设计7段数码是纯组合电路,通常的小规模专用IC,如74或4000系列的器件只能作十进制BCD码译码,然而数字系统中的数据处理和运算都是二进制的,所以输出表达都是十六进制的,为了满足十六进制数的译码显示,最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器,输出信号LED7S的7位分别接数码管的7个段,高位在左,低位在右。例如当LED7S输出为“1101101”时,数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1;接有高电平的段发亮,于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
- 2022-08-11 21:55:01下载
- 积分:1
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SRAM 简单测试
SRAM简单测试,测试其性能及其速度,判断SRAM是否可用(Test its performance and speed to determine if SRAM is available)
- 2020-07-10 09:58:55下载
- 积分:1