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四人抢答器,已通过编译,仿真,包括抢答识别、计分、计时、数字显示等功能。...
四人抢答器,已通过编译,仿真,包括抢答识别、计分、计时、数字显示等功能。-Four Responder, has passed the compilation, simulation, including the answer in his identification, scoring, timing and digital display.
- 2023-08-16 08:05:03下载
- 积分:1
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pc_cfr_test_v3_1c
一个关于降低现代通信系统中高峰均比信号的matlab算法,对于研究数字预失真基于FPGA实现的有一定作用!(A modern communication system on the lower than the peak signal matlab algorithm for FPGA-based study of digital pre-distortion to achieve a certain effect!
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- 2011-07-07 22:01:17下载
- 积分:1
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Listingprogram1
listing program clock
- 2012-11-26 03:31:42下载
- 积分:1
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pc104接口的verilog代码,仅供参考
pc104接口的verilog代码,仅供参考-pc104 verilog interface code for reference purposes only
- 2022-12-27 10:00:03下载
- 积分:1
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Cadence VHDL Operational the package, seeking to achieve root, You are not squar...
Cadence的VHDL运算库包,实现求方根,平方你是不是以前不知道怎么弄.哈哈.-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
- 2022-08-16 03:35:39下载
- 积分:1
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ser_to_parr
很有用的10bit串并转换verilog程序,需要的可以拿去参考下,在quartusII上已验证过(Useful 10bit string and convert verilog program, need to take a reference, has been verified in quartusII)
- 2012-05-21 16:21:22下载
- 积分:1
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lab2
说明: 使用vivado和Xilinx开发板实现抢答器,开发板为Xilinx Artix-7(Using vivado and Xilinx development board to achieve the responder, the development board is Xilinx artix-7)
- 2021-04-23 01:58:48下载
- 积分:1
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3FP
一个三分频verilog模块,可以用来学习基本结构。(A three points frequency verilog module can be used to study the basic structure.)
- 2013-08-25 00:41:29下载
- 积分:1
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在 VHDL 中的离散余弦 Transform(DCT/IDCT)
项目目的是设计 DCT 和 IDCT 在 VHDL 中。离散余弦变换图像压缩中用于压缩的 JPEG 图像。此文件包含 DCT 和 IDCT 块和顶级模块于一体的两个块和矢量来测试这两个模块。
- 2022-02-05 11:13:18下载
- 积分:1
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这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核,文档齐全...
这个是专门用在ALtera第二代PLD MAXII上的16位微处理器IP核,文档齐全-this is the ALtera devoted second-generation PLD MAXII on the 16-bit microprocessor IP core, complete documentation
- 2022-02-21 05:05:05下载
- 积分:1