-
IDT7005
双端口静态RAM的VHDL程序，具体芯片型号为IDT7005(DUAL-PORT
STATIC RAM)
- 2014-04-03 11:40:53下载
- 积分：1
-
design-of-CAN-based-on-VHDL
基于Verilog+HDL设计CAN控制器,详细介绍各功能模块的设计。本论文的重点是CAN总线通信控制器的前端设计。即用Verilog HDL语言完成CAN协议的数据链路层的RTL级设计，实现其功能，并且能够在FPGA开发平台Quartos上通过仿真验证，证明其正确性(Verilog+ HDL-based design of CAN controller, detailed design of each functional module. This paper focuses on the CAN bus communication controller front-end design. Verilog HDL language that is used to complete the data link layer CAN protocol the RTL-level design, to achieve its function, and can be on the FPGA development platform Quartos by simulation to prove its correctness)
- 2011-07-22 15:22:27下载
- 积分：1
-
用于fpga学习，共同分享学习经验和交流学习心得
用于fpga学习，共同分享学习经验和交流学习心得-For fpga to learn, to share learning experiences and the exchange of learning
- 2022-02-25 22:21:38下载
- 积分：1
-
merry-go-round
能够成功的实现走马灯功能，使LED循环亮灭(To succeed the implementation of the version function, make the LED circular light out)
- 2013-06-13 22:45:50下载
- 积分：1
-
Verilog HDL数字设计与综合 夏宇闻译（第二版）
电子书籍 verilog HDL 数字设计与综合 夏宇闻所编写(electronic text
Foreign electronic and communication textbooks)
- 2021-01-15 15:18:45下载
- 积分：1
-
cnt
在ise开发环境下，建立顶层模块和子模块的层次结构，其实现的功能是一个可复位课暂停开始继续的建议秒表(In ise development environment, establish a hierarchy of top-level modules and sub-modules, and its function is to achieve a resettable class resumes proposal to suspend the stopwatch)
- 2014-11-03 19:35:21下载
- 积分：1
-
buffer
用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)
- 2020-10-28 12:19:58下载
- 积分：1
-
XilinxISE9.2andChinpScopePro9.2Sn
Xilinx ISE 9.2 and ChinpScope Pro 9.2 Sn
- 2021-03-29 15:29:11下载
- 积分：1
-
FIFO
This is a simple example of FIFO(first in and first out) module written in verilog code(This is a simple example of FIFO (first in and first out) module written in verilog code)
- 2013-10-04 00:41:42下载
- 积分：1
-
Clifford-E.-Cummings-paper
Clifford E. Cummings论文合集，其中关于FIFO的设计很经典(Clifford E. Cummings collection of papers, on the FIFO design classic)
- 2012-07-21 01:32:34下载
- 积分：1
