登录
首页 » VHDL » this come from alter ,you can look and find it on line about USB

this come from alter ,you can look and find it on line about USB

于 2023-09-06 发布 文件大小:86.88 kB
0 228
下载积分: 2 下载次数: 1

代码说明:

this come from alter ,you can look and find it on line about USB

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • DSP--PFPGA
    在FPGA中编写FPGA芯片与DSP28335进行通信的程序(FPGA chip and DSP28335 written in FPGA communication program)
    2015-02-02 18:46:25下载
    积分:1
  • 设计一个可以小时、分钟、12小时或24小时和秒的时间…
    设计一个能进行时、分、秒计时的十二小时制或二十四小时制的数字钟,并具有定时与闹钟功能,能在设定的时间发出闹铃音,能非常方便地对小时、分钟和秒进行手动调节以校准时间,每逢整点,产生报时音报时。 实验平台: 1. 一台PC机; 2. MAX+PLUSII10.1。 Verilog HDL语言实现,还有完整的实验报告-The design of a can be hours, minutes, seconds time of 12 hours or 24 hours system, digital clock, and has from time to time with the alarm clock function, can be set to issue a sound alarm can be very convenient to hours, minutes and seconds for manual adjustment to calibrate the time, whenever there is the whole point, resulting in timekeeping timekeeping tone. Experimental platform: 1. A PC machine 2. MAX+ PLUSII10.1. Verilog HDL language, as well as a complete experimental report
    2022-07-22 15:10:59下载
    积分:1
  • mike11xns
    mike11河道断面处理软件,将断面格式写成11要求的格式(MIKE11 river section processing software, the section format 11 format )
    2021-04-06 17:29:02下载
    积分:1
  • vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0...
    vhdl,序列信号检测模块,此模块检测1110010,可改为任意序列,输出电位为1为检测出,否则为0-vhdl, sequence of signal detection module, this module testing 1.11001 million, can be changed to an arbitrary sequence, the output potential of an as detected, otherwise 0
    2022-10-12 22:25:03下载
    积分:1
  • EDAcodelock
    能够在EDA环境下实现四位十进制数字密码锁的设置与开锁功能,并能更改使用密码,还可以防止抖动(EDA environment to achieve four decimal code lock and unlock function of the settings and change the use of passwords, but also to prevent the jitter)
    2009-05-07 09:44:30下载
    积分:1
  • RS_Encode_Decode
    RS(255,223)编解码算法。verilogHDL代码实现,在XILINX的芯片上得到验证。不包含任何IP核,方便移植到任何FPGA芯片。(RS (255223) encoding and decoding algorithm. VerilogHDL code to achieve, in the XILINX chip to be verified. Does not contain any IP core, easy to transplant to any FPGA chip.)
    2016-01-21 12:07:34下载
    积分:1
  • SPI FLASH的控制器,FPGA实现,VHDL
    SPI FLASH的控制器,FPGA实现,VHDL 对于想使用FPGA实现spi flash控制的同学应该有用
    2022-03-23 23:56:51下载
    积分:1
  • 行人交通灯系统设计与7段显示
    2022-08-09 10:50:36下载
    积分:1
  • shape
    基于FPGA的成型滤波器的代码,里面内附激励文件,使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)
    2014-06-05 16:52:06下载
    积分:1
  • adder8
    8位加法器源代码,vivado实现编写。(8 adder Source, vivado achieve write.)
    2015-12-01 20:35:55下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载