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ALTERA NIOS处理器实验,编程环境是QUARTUS,在NIOS SHELL下编译实现功能。实验USB接口...
ALTERA NIOS处理器实验,编程环境是QUARTUS,在NIOS SHELL下编译实现功能。实验USB接口-Altera NIOS processor experiments, programming environment is QUARTUS in NIOS SHELL compiler functionality. Experimental USB interface
- 2022-05-25 15:09:52下载
- 积分:1
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VHDL-100-examples
VHDL 的100例程代码,能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)
- 2012-07-31 11:17:51下载
- 积分:1
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本书详细介绍了VHDL硬件描述语言,希望在以后的工作中能用到...
本书详细介绍了VHDL硬件描述语言,希望在以后的工作中能用到-This book details the VHDL hardware description language, want to work in the future can be used to
- 2022-05-25 00:38:07下载
- 积分:1
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project_1
说明: 简单的一个Verilog小程序,适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分:1
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altera详细使用配置手册,有一定的参考价值,写的比较详细
altera详细使用配置手册,有一定的参考价值,写的比较详细-altera in detail the use of manual configuration, has a certain reference value, a more detailed written
- 2022-03-20 13:35:35下载
- 积分:1
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chuankou
本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
- 2020-06-24 01:40:02下载
- 积分:1
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计数器的VHDL语言
这个程序VHDL计数器计数二进制数并显示脉冲易于程序计数器的VHDL,我们需要了解逻辑电路的VHDL语言的程序员
- 2022-12-04 13:20:03下载
- 积分:1
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fifo
一个FIFO产生程序,主要是一个格雷码的加法器(A FIFO generation process, is primarily a gray code adder)
- 2011-08-28 10:39:31下载
- 积分:1
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以太网MAC core.this是etherenet UDP的应用
ethernet mac core.this is the etherenet udp application
- 2022-02-10 06:08:39下载
- 积分:1
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dianyuan
实现按键控制AD三通道的电源转换的功能。(AD three buttons control channel to achieve power conversion)
- 2015-04-23 16:20:49下载
- 积分:1