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yuandaima
以GPS为时间基准，实现多传感器器数据同步采集，整合信息后发送 VERILOG语言编写 QUARTUS II环境(GPS-time basis, synchronized multi-sensor data acquisition, integration of information after sending VERILOG language environment QUARTUS II)
- 2014-10-12 19:15:45下载
- 积分：1
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DSP--PFPGA
在FPGA中编写FPGA芯片与DSP28335进行通信的程序(FPGA chip and DSP28335 written in FPGA communication program)
- 2015-02-02 18:46:25下载
- 积分：1
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CPU-master
misp，五级流水源码，实现一个建议的cpu(Misp, five-stage flow source code, implementation of a recommended CPU)
- 2020-06-16 00:00:07下载
- 积分：1
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ymq.ppt.tar
掌握二-十进制(BCD码)异步计数器的工作原理和设计方法；
掌握中规模集成二-五-十进制异步计数器74LS90的功能及其应用；(Master II- Decimal (BCD code) the principle and an asynchronous counter design grasp the scale of integration in two- five- Decimal asynchronous counter 74LS90 features and applications )
- 2011-04-26 21:53:37下载
- 积分：1
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This is the design of the divider module EDA. Can achieve three different freque...
此为EDA设计的分频器模块。可以实现三种不同的频率信号，可以通过使用者自由设置频率大小-This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of
- 2022-07-22 16:48:57下载
- 积分：1
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VHDL language is designed to be simple to use the CPU, the focus of the design o...
用VHDL语言设计简单的CPU，重点设计微操作代码，然后设计CPU各组成模块，最后根据设计的微操作设计微指令，验证设计的正确性。可基本实现加、减、乘、除、移位、循环等操作。-VHDL language is designed to be simple to use the CPU, the focus of the design of micro-operation code, and then design the components of CPU module designed the final design of the micro-operation microinstruction to verify the correctness of the design. Can achieve the basic add, subtract, multiply, divide, transfer, recycling and other operations.
- 2022-01-26 04:06:25下载
- 积分：1
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16QAM
基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)
- 2021-02-23 23:49:39下载
- 积分：1
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8位7段LED显示源码，扫描显示，稳定高效
8位7段LED显示源码，扫描显示，稳定高效-seven of the eight LED source, scanning, stable and efficient
- 2022-02-15 21:05:29下载
- 积分：1
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EMIF
EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功(EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success)
- 2020-12-04 10:39:24下载
- 积分：1
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64point_FFT
64点FFT代码 基4算法 Verilog(64-point FFT code radix-4 algorithm Verilog)
- 2021-01-15 09:48:46下载
- 积分：1
