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vga接口的工程实现，基于altera环境，需要的可以
vga接口的工程实现，基于altera环境，需要的可以-vga interface engineering implementation, based on altera environment, need to take a look at
- 2023-04-22 21:05:04下载
- 积分：1
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UART
verilog代码，串口发送接收代码，含有源代码和测试文件，准确可用(verilog code for serial port transmit and receive code, with source code and test files, and accurate available)
- 2011-10-19 09:20:12下载
- 积分：1
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LaSaNewNB_M88E1111_TCP1000mhz
用FPGA，基于M88E1111芯片实现的TCP/IP协议的千兆网，将协议封装成IP核(With the FPGA, the TCP/IP protocol based on the M88E1111 chip is used to encapsulate the protocol into IP core)
- 2018-02-08 13:23:07下载
- 积分：1
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Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, en...
基于状态图的光电编码器4倍频vhdl程序，输入相位差90度的两相，输出倍频和方向信号-Based on the state of the optical encoder Figure 4 multiplier vhdl procedure, enter a 90-degree phase difference of two-phase, frequency and direction of the output signal
- 2022-03-17 02:46:02下载
- 积分：1
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NIOSIIREV5.0
很好的学习FPGA嵌入式的资料！适合初学者和工程师参考！(Good learning FPGA embedded information! Suitable for beginners and engineers reference!)
- 2013-08-10 17:24:50下载
- 积分：1
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regress-900055
The Date prototype object is itself a Date object (its [[Class]] is "Date") whose value is NaN.
- 2013-12-27 00:29:58下载
- 积分：1
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数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84...
数字秒表的VHDL设计,能精确到百分秒,在6位数码管上显示,分别有秒,分,小时,通过目标芯片EPF10KLC84-4验证-VHDL design of digital stopwatch, accurate to the percentage of seconds in the six digital tube display, respectively, have seconds, minutes, hours, through the target chips EPF10KLC84-4 verification
- 2022-07-20 17:58:12下载
- 积分：1
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decode
用Verilog实现汉明码编码，经测试可正确使用，代码简洁(Verilog with Hamming code encoding, the test can be used correctly, the code is simple)
- 2017-03-10 19:28:21下载
- 积分：1
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使用VHDL在CPLD上设计UART的一个项目
使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
- 2023-05-10 12:20:04下载
- 积分：1
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VHDL
先设计序列发生器产生序列：1011010001101010；再设计序列检测器，检测序列发生器产生序列，若检测到信号与预置待测信号相同，则输出“1”，否则输出“0”，并且将检测到的信号的显示出来。(First design sequence generator sequence: 1011010001101010 redesign sequence detector to detect sequence generator sequence, if the same signal is detected with the preset test signal output " 1" , otherwise " 0" , and the detection display signal out.)
- 2015-01-04 12:35:54下载
- 积分：1
