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UART
实现了UART的底层协议，加入了控制器，其波特率可以根据使用进行调整；发送模块、接收模块相互独立，互不影响。(Realization of the underlying protocol UART, joined the controller baud rate can be adjusted according to use transmission module, receiver module are independent of each other.)
- 2013-11-30 13:25:21下载
- 积分：1
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基于DE2-70开发板的VGA接口实现程序
基于DE2-70开发板的VGA接口实现程序，可在VGA屏幕上显示800*600分辨率的图像，刷新频率60Hz
- 2022-03-12 13:00:51下载
- 积分：1
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sobel
Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现(Verilog，Sobel Operator)
- 2011-05-10 21:11:21下载
- 积分：1
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BCD-counter
一个2位的BCD码十进制加法计数器电路，输入为时钟信号CLK，进位
输入信号CIN，每个BCD码十进制加法计数器的输出信号为D、C、B、A和进位输出信号COUT，输入时钟信号CLK用固定时钟，进位输入信号CIN.
(A 2-bit BCD code decimal adder counter circuit input as the clock signal CLK, a carry input signal CIN, D, C, B, A, and the carry output signal COUT, each BCD code decimal adder counter' s output signal, the input clock signal CLK Fixed clock, binary input signal CIN.)
- 2020-10-28 19:29:58下载
- 积分：1
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关于两种实现pwm的方法 基于51单片机设计
关于两种实现pwm的方法 基于51单片机设计-on two methods to achieve PWM 51 microcontroller-based design
- 2022-01-26 05:09:13下载
- 积分：1
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dot_product
实现矩阵相乘，即点积运算，为VERILOG语言。可以根据自己的需要改变维数，采用了流水线的结构(Achieve matrix multiplication, ie dot product operations, for VERILOG language. You can change the dimension according to their needs, using a pipeline structure)
- 2015-01-27 10:52:52下载
- 积分：1
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vhdl adder with two input 4
vhdl adder with two input 4-bit and output of 4 bits and carry
- 2022-11-16 00:35:03下载
- 积分：1
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我的学习经验，一种自适应分频及分频方法的实现，很好用的哦...
我的学习经验，一种自适应分频及分频方法的实现，很好用的哦-my learning experience, an adaptive frequency-frequency method and the realization of the good, oh
- 2022-02-03 01:08:00下载
- 积分：1
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Version1
小波包分解，重构轴承振动信号，Hilbert包络，FFT进行频谱分析，以获得轴承故障频率。(Wavelet packet decomposition, reconstruction of bearing vibration signal, Hilbert envelope, FFT spectrum analysis to obtain the bearing fault frequencies.)
- 2013-07-17 11:37:05下载
- 积分：1
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cpu-maxplus
MaxplusII编写的简易cpu，可实现简单加减法等操作(MaxplusII summary prepared by the cpu can realize simple addition and subtraction, etc)
- 2007-06-08 17:55:10下载
- 积分：1
