-
三种方法编写多路选择器的VHDL源代码
分别使用if else ,select ,when 语句...
三种方法编写多路选择器的VHDL源代码
分别使用if else ,select ,when 语句-three methods to prepare multiple choice of VHDL source code were used if else, select, when words
- 2023-02-04 23:35:03下载
- 积分:1
-
three_motor
matlab仿真MATLAB电机仿真精华50例--源代码异步电机\asymotor_stator.mdl
- 2010-01-16 22:02:43下载
- 积分:1
-
half_adrrrrder
FPGA上的一个半加器实例程序,通过测试,可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)
- 2013-12-01 12:01:31下载
- 积分:1
-
rs232_3
说明: 为串口收发器以及汉明编码,将电脑通过串口发送的7位数据转化成汉明码显示于led上,或把接收到的11位汉明码解码并验错纠错(For the serial port transceiver, and Hamming codes, the computer through the serial port into 7-bit data displayed on the led on the Hamming code, or to receive the 11 Hamming code error correction decoding and experience)
- 2010-04-29 22:18:02下载
- 积分:1
-
自己编写的经过QuartusII验证的Verilog HDL程序,可以实现常见功能...
自己编写的经过QuartusII验证的Verilog HDL程序,可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features
- 2022-01-23 10:27:24下载
- 积分:1
-
Viterbi译码器IP核,可以直接编译使用
viterbi译码器的IP核,可以直接编译使用-viterbi decoder IP core, the compiler can directly use
- 2023-01-24 09:35:04下载
- 积分:1
-
frame_decode_and_encode
一个用Verilog编写的编帧、解帧及码速匹配的程序,相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)
- 2006-07-12 15:10:07下载
- 积分:1
-
fir_vivado
此压缩包里面有基于vivado平台的工程,包括了正弦信号的产生,还有fir滤波器的设计以及fft算法的设计实现(in this package,there are three projects of
the generation of the signal of sin and the
design of fir filter and the ari)
- 2016-09-18 15:00:22下载
- 积分:1
-
Design and Implementation of the SNMP Agents
A programming language that can decode alpha numeric
- 2018-12-06 10:15:01下载
- 积分:1
-
vhdl子程序,本人收集的,比较常用的代码
vhdl子程序,本人收集的,比较常用的代码-VHDL subprogram, I collected to compare commonly used code
- 2022-04-14 14:19:05下载
- 积分:1