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Describes how to use VHDL language processor spi interface
介绍了如何用vhdl语言实现处理器的spi接口-Describes how to use VHDL language processor spi interface
- 2022-07-22 21:57:12下载
- 积分：1
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dpll
用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证(verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider )
- 2014-04-22 08:36:53下载
- 积分：1
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dpll
说明： 在quartus下搭建的数字锁相环，能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)
- 2020-06-21 01:00:02下载
- 积分：1
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here is realized simple FIFO stack in vhdl.
very simple example, but very help...
here is realized simple FIFO stack in vhdl.
very simple example, but very helpful.
- 2022-03-12 07:44:59下载
- 积分：1
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基于Verilog的FFT核
- 2022-10-27 16:20:03下载
- 积分：1
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03-verilog-11
Verilog reference book
- 2015-02-06 09:03:48下载
- 积分：1
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PC9054_1124
基于FPGA的PCI9054 LOCALBUS总线接口(PCI9054 interface program based on FPGA)
- 2015-04-07 09:44:02下载
- 积分：1
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fifo
异步FIFO
输入: 16bit
输出:16bit
深度:256(Asynchronous FIFO
Input: 16bit
Output: 16bit
Depth: 256)
- 2017-07-10 14:02:36下载
- 积分：1
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频率计实验程序代码
说明： XC7A35TCSG324-1的Verilog频率计程序，支持十分频，支持切换内外信号输入(Verilog frequency meter program of xc7a35tcsg324-1 supports decadal frequency division and switching internal and external signal input)
- 2019-12-24 13:40:45下载
- 积分：1
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med01-165
median filter details
- 2011-01-30 18:29:06下载
- 积分：1
