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multiplier.tar
用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过(Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass)
- 2021-04-14 13:18:55下载
- 积分：1
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3-8
3-8译码器，可以讲三位二进制输入转换为8中取1的输出信号(3-8 decoder, you can talk about the three binary input is converted to 8 of the output signal from 1)
- 2009-07-16 17:23:30下载
- 积分：1
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ＶＨＤＬ编写的flash控制器源代码.包含testbench。
ＶＨＤＬ编写的flash控制器源代码.包含testbench。-Prepared by flash controller VHDL source code. Contains testbench.
- 2022-03-18 10:11:40下载
- 积分：1
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C54x is the Verilog code opencoreip
c54x的VeriLog程序代码
也是opencoreip-C54x is the Verilog code opencoreip
- 2022-03-26 18:08:34下载
- 积分：1
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FPGA to design in ECU, very help for engineer
FPGA to design in ECU, very help for engineer
- 2022-05-27 17:19:39下载
- 积分：1
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ethmac10g_latest.tar
10G高速以太网mac VERILOG源码
可仿真可实现(10G high speed Ethernet MAC verilog code
can be used for synthesis or inplementation)
- 2015-08-19 17:39:02下载
- 积分：1
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FSK_FPGA
FSK模拟信号源，利用ISE7.1或以上环境打开。(FSK signal simulator.The project can be open in ISE7.1 or upgrade version.)
- 2009-07-16 17:09:07下载
- 积分：1
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Ffpga-jpegP
基于FPGA的JPEG图像压压缩，实现JPEG图像的实时压缩
(Real-time compression pressure compressed FPGA-based JPEG images, JPEG images)
- 2012-08-23 22:11:39下载
- 积分：1
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Gen_Opto_Simplis
Simetrix搭建的一个光传输仿真工程，很好的学习参考。(Simetrix built an optical transmission simulation project, a good reference for learning.)
- 2018-09-15 00:22:03下载
- 积分：1
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shizhong
VHDL写时钟，分频模块什么，实现计时。定点报时，定点闹钟，显示年月日。(verilog HDL)
- 2014-01-09 18:29:40下载
- 积分：1
