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STOPWATCH
STOPWATCH FPGA SEVEN SEGMENT DISPLAY
- 2014-04-16 11:08:57下载
- 积分：1
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DCM
fpga DCM使用教程 好几个文档 帮助您一次学会使用DCM(fpga the DCM using the tutorial a few documents to help you first learn to use the DCM)
- 2012-04-23 16:59:20下载
- 积分：1
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用FPGA实现数字锁相环，开发环境为ISE
用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE
- 2022-06-22 05:34:34下载
- 积分：1
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piano_final
ASK,FSK,PSK,DPSK调制解调的详细仿真代码(ASK, FSK, PSK, DPSK modulation and demodulation detailed simulation code)
- 2021-02-26 16:49:37下载
- 积分：1
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UART
说明： 串口通信vivado实现，带有仿真文件，可实现数据收发(the uart program based on vivado)
- 2020-07-02 16:15:57下载
- 积分：1
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dual_ram
说明： FPGA和双端口RAM的DDS任意波形发生器的实现(FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator)
- 2009-07-27 16:32:36下载
- 积分：1
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chap12
《Verilog HDL 程序设计教程》9("Verilog HDL Design Guide" 9)
- 2007-07-01 16:33:31下载
- 积分：1
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8bit-cpu
VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计(VHDL realization 8 of cpu design)
- 2015-10-16 14:26:34下载
- 积分：1
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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
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XILINX FPGA on internal training materials in Chinese
关于XILINX FPGA
内部
中文培训教材-XILINX FPGA on internal training materials in Chinese
- 2022-05-22 03:01:00下载
- 积分：1
