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ldpc_decoder_802_3an
LDPC的编码模块和解码模块,实现802-3an协议的编码(The module of LDPC to implement the coding of the 802-3an protocol)
- 2018-07-23 15:01:20下载
- 积分:1
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内嵌BRAM设计LIFO堆栈
具有先进后出的堆栈功能。此LIFO堆栈具有两个按键(write, read),按下write键后,开始输入数据data0-data3;按下read键后,7段数码管开始倒序显示data3-data0(十进制)。
高级要求(可选): 按下write键,VGA显示“Write”字样,并同时显示输入数据;按下read键,VGA显示“Read”字样,并同时显示输出数据。
- 2022-04-29 13:49:12下载
- 积分:1
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verilog program for iic bus design. the pakege includes iic protocl master progr...
Verilog数字系统设计教程【夏宇闻】原书第十章:IIC总线接口模块设计代码包-verilog program for iic bus design. the pakege includes iic protocl master program and behavel slavle program, even includes testbench and data bat files.
- 2022-01-31 13:13:45下载
- 积分:1
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simple eight CPU, containing PDF files. They can check details
简单的8个CPU,包含PDF文件。他们可以查看详细信息
- 2022-07-03 13:41:23下载
- 积分:1
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RS
说明: 通过verilog hdl语言实现RS编码器与译码器的设计(Verilog hdl language through the RS encoder and decoder design)
- 2013-07-18 16:09:22下载
- 积分:1
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ads1278_fpga
说明: 八通道ad采集,用于和fpga的联调测试,需要注意ADS1278的模式类型(Eight channel AD acquisition)
- 2021-01-06 16:59:02下载
- 积分:1
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Hardware-CNN-master
Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分:1
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SOS
使用matlab生成SOS滤波器,应用于FPGA的一个小型系统,有一定的参考价值(Using MATLAB to generate SOS filter, applied to a small system of FPGA, there is a certain reference value)
- 2016-07-31 20:53:19下载
- 积分:1
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用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core....
用walsh算法实现的符号数乘法器,asic流片时,可以不用公司的付费乘法器的ip core.-algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company"s paid Multiplier ip core.
- 2022-03-30 14:40:42下载
- 积分:1
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Verilog 经典实例,完整源码与大家分享
Verilog 经典实例,完整源码与大家分享-Verilog classic example of a complete source to share with you
- 2022-07-03 12:56:56下载
- 积分:1