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FPGA realize for a good vga display routines, vhdl language.
针对FPGA一个实现vga显示的很好的例程，vhdl语言编写。-FPGA realize for a good vga display routines, vhdl language.
- 2022-01-24 09:45:51下载
- 积分：1
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FPGA
基于FPGA的图像采集卡的设计与相关说明-FPGA-based design of frame grabbers and related note
- 2023-06-09 09:00:04下载
- 积分：1
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802-11-Frame_E_C
Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a
station in Power Save mode
- 2016-08-23 17:37:40下载
- 积分：1
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pingpong
用Verilog代码实现的乒乓操作，用Verilog代码实现的乒乓操作(Verilog pingpong)
- 2016-01-15 17:35:06下载
- 积分：1
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spi flash 控制器设计
基于FPGA的spi flash 控制器设计，详细的vhdl代码分析.......................................................................................................................................................................................................................
- 2022-07-04 03:02:41下载
- 积分：1
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divisor
Time divisor vhdl code
- 2009-06-02 21:31:05下载
- 积分：1
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edc_spi_command
单片机和FPGA的通信程序，发送5个数，传输稳定，可以自行修改可一次传多个数(MCU and FPGA communication program, send five the number of stable transmission, you can modify the number may be more than one pass)
- 2013-09-14 21:09:52下载
- 积分：1
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VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
VHDL_APPOINTMENT TIME(Hẹn thời gian hiển thị LCD sử dụng ngôn ngữ VHDL)
- 2022-01-25 18:25:54下载
- 积分：1
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BNN-PYNQ-master
在PYNQ-Z1上搭建二值神经网络(BNN)(Building two value neural network (BNN) on PYNQ-Z1)
- 2018-01-15 11:34:33下载
- 积分：1
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使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭...
使用VHDL语言，对Altera公司的DE2开发板进行开发，本例实现了对板上7段数码管的显示，在niosiiIDE上基于硬件实现小灯的循环亮灭-Using VHDL language, on Altera s DE2 development board for development, which in this case the realization of paragraph 7 of the on-board digital tube display, in niosiiIDE hardware implementation based on a small circle of bright lights out
- 2022-03-17 06:00:39下载
- 积分：1
