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asynchronous-fifo
同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分：1
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DE2_LCM_DISP_sucess
这是altera公司的DE2-35开发板下的一个液晶显示屏源程序代码工程，液晶显示屏是友晶公司的，包括液晶显示屏的驱动以及显示等模块有需要的人，可以下载
(Altera DE2-35 development board of the company, a liquid crystal display source code engineering, LCD display the Terasic, including LCD driver module and display needs, you can download)
- 2012-10-19 21:04:47下载
- 积分：1
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Using Verilog to write a serial transmission to the parallel transmission of the...
一个用verilog写的串行传输到并行传输的程序，在quaters下编的-Using Verilog to write a serial transmission to the parallel transmission of the procedure, under the quaters
- 2022-06-14 12:50:53下载
- 积分：1
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AD7768 Verilog Driver
说明： 8通道24Bit同步A/D芯片AD7768的SPI接口例程(SPI interface routine of 8-channel 24bit synchronous A / D chip ad7768)
- 2020-01-10 21:13:21下载
- 积分：1
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数字信号处理的FPGA实现-第三版-verilog源程序
数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
- 2017-08-06 17:38:33下载
- 积分：1
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FFT
verilog xilinx IP实现FFT仿真(Verilog xilinx IP implementation FFT simulation)
- 2017-03-14 00:15:29下载
- 积分：1
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clock_smg
自己做的数码管显示的时钟 一个非常简单的FPGA时钟 用累加做的(To do their own digital display clock of the FPGA clock is a very simple to do with the cumulative)
- 2011-09-27 21:07:54下载
- 积分：1
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SSI-ABZ
SSI转ABZ信号FPGA程序，测试完全可用(Function of SSI convert to ABZ signal,is available)
- 2019-05-19 15:37:48下载
- 积分：1
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gcounter1
数字钟vhdl实现，在线测试无误，具有闹钟，对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)
- 2013-10-19 22:06:16下载
- 积分：1
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FPGA
基于fpga的多功能电子钟的设计非常使用希望对大家有帮助啊-FPGA-based multi-functional electronic clock design to use would like to help everyone ah
- 2023-06-23 00:15:03下载
- 积分：1
