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8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量...
8051内核的hdl代码，实际上是verilog格式不过上载页面只有一个vhdl选择，值得一读， 里面对仿真和验证的说明很有含金量-the hdl code of 8051 core
- 2022-08-08 19:01:35下载
- 积分：1
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NN-using-FPGA
thesis about design and implementation neural network using FPGA
- 2013-12-29 16:23:52下载
- 积分：1
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RISC
说明： RISC全部源码，包含仿真文件，使用makefile脚本编写，能通过vcs编译(RISC all source code, including simulation files, using makefile script, can be compiled through VCS)
- 2020-04-14 22:10:52下载
- 积分：1
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The time of the year undergraduate graduate design, signal generator and frequen...
当年本科时的毕业设计，信号发生器和频率计-The time of the year undergraduate graduate design, signal generator and frequency counter
- 2023-08-01 18:30:02下载
- 积分：1
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GMSK调制基带眼图仿真源代码
GMSK调制基带眼图仿真源代码，基于MATLAB(GMSK modulation baseband eye diagram simulation source code, based on MATLAB)
- 2020-06-28 11:40:01下载
- 积分：1
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This is achieved using VHDL positive and negative pulse width modulator, the sam...
这个是用VHDL实现的正负脉宽调制器，同样是对新手有帮助，高手不必看了。-This is achieved using VHDL positive and negative pulse width modulator, the same is to help novice, you do not have to read. Ha ha
- 2022-06-19 04:51:41下载
- 积分：1
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04_ep2c8_vga_test
VIP FPGA板的配套例子，这个是VGA格式lcd液晶屏幕显示用。(VIP board supporting example of this is the VGA format PREVIEW.)
- 2013-10-18 19:03:37下载
- 积分：1
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fft_16
16点FFT，简单易理解，适合初学者了解(16 point FFT, simple and easy to understand, suitable for beginners to understand)
- 2018-05-07 16:20:10下载
- 积分：1
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RTC
verilog编写的RTC（实时时钟）包含APB总线接口、时钟计时部分等(verilog prepared by the RTC (real time clock) contains APB bus interface, clock time some other)
- 2009-12-19 23:51:50下载
- 积分：1
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CXFlt
通信系统中的基带信号处理中的成型滤波器代码，已经通过编译。(Communication system baseband signal processing shaping filter code, has passed the compilation.)
- 2015-03-24 09:43:05下载
- 积分：1
