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FPGA_four_num_code_lock
说明： 基于EasyFPGA030的四位数字密码锁。(Based on the four-digit lock EasyFPGA030.)
- 2010-04-29 15:16:29下载
- 积分：1
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USB转RS232
USB转RS232RSTTLRS485FT232+SP213串口的原理图AD画的(USB to RS232RSTTLRS485FT232+SP213 serial port schematic AD drawing)
- 2020-07-01 04:20:02下载
- 积分：1
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vhdl程序集
本人初学VHDL时编的比较系统的VHDL源程序 巨实用 (I am learning more systematic series of practical VHDL source Giant)
- 2005-03-09 15:17:21下载
- 积分：1
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This is what I did do a UART transmitter when the source and hope for all of us.
这是我做UART时候做的一个发送器的源码，希望对大家有用。-This is what I did do a UART transmitter when the source and hope for all of us.
- 2022-03-25 00:51:09下载
- 积分：1
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PWM
verilogHDL语言编写，简单的FPGA脉冲程序，初学者必备。(verilogHDL language, a simple FPGA pulse program, beginners must.)
- 2012-12-27 11:54:45下载
- 积分：1
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VHDL4人抢答器
4人抢答系统，可以计时20秒，20秒无人抢答则视作无人抢答。start之前抢答者视为违规抢答，违规抢答会警告选手。若有一人抢答则其他3人锁定，不可再抢答。aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa
- 2022-03-17 00:58:23下载
- 积分：1
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基于fpga的DDS程序 AD9767
基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)
- 2020-06-20 21:00:01下载
- 积分：1
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DDR_interface
高速DDR存储器数据接口设计实例.
1. 将文件拷入硬盘
2. 产生DQS模块
3. 产生DQ模块
4. 产生PLL模块
5. 拷贝以上步骤生成的文件到子目录【Project】中
6. 打开子目录【Project】中的DataPath.qpf工程，设计顶层模块
7. 编译并查看编译结果
(High-speed DDR memory interface design data. 1. Copyed into the document hard disk 2. DQS generated module 3. Have a DQ module 4. Have a PLL module 5. Copies of the above steps to generate a document to a subdirectory 【Project】 6. Open the subdirectory 【Project】 DataPath.qpf in engineering, design top-level module 7. compilers to compile the results and see)
- 2009-04-27 11:52:56下载
- 积分：1
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verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用....
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-08-24 07:12:53下载
- 积分：1
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SystemOfTaxiFeeBasedOnVerilogHDL
摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。
关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分：1
