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图书馆的IEEE
LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL
USE IEEE.STD_LOGIC_ARITH.ALL
USE IEEE.STD_LOGIC_UNSIGNED.ALL
- 2022-03-24 00:58:30下载
- 积分:1
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VC707_MIG_DDR3
说明: VC707_MIG_DDR3.sim文件夹中是仿真的文件:testbench和DDR3模型参数
VC707_MIG_DDR3.srcs文件夹中是源文件,包含DDR3的控制、收发模块、顶层文件(VC707_ MIG_ In ddr3.sim folder are simulation files: testbench and DDR3 model parameters
VC707_ MIG_ Ddr3.srcs folder is the source file, including DDR3 control, transceiver module, top-level file)
- 2020-10-16 19:20:53下载
- 积分:1
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ulpi_port
ULPI UTMI conversion
- 2015-03-12 14:59:25下载
- 积分:1
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30
说明: 30 bus for atp design
- 2016-02-14 19:41:55下载
- 积分:1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟,计数器进行加计数,并利用数码管进行显示,当计数到9999 时,从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分:1
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vga_ctl_640x480
VGA 640x480 driver in verilog
- 2010-08-16 02:48:43下载
- 积分:1
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fpga VHDL语言,控制DDS产生频率可变的正弦波信号扫频
fpga VHDL语言,控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS
- 2022-06-29 15:53:56下载
- 积分:1
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一个异步FIFO的verilog实现论文
一个异步FIFO的verilog实现论文-err
- 2022-01-28 06:08:18下载
- 积分:1
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Continuous_acoustic_emission_board
说明: 多通道连续声发射数据采集,每个通道最大5M,采用verilog编程,内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)
- 2020-06-25 13:00:01下载
- 积分:1
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Xilinx vivado authoritative course
Xilinx vivado 权威教程,清华大学出版社出版,何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)
- 2019-02-19 20:37:09下载
- 积分:1