-
new
vivado2017.4下的串口通信的Verilog源码，一次传输8位，包括发送模块，接受模块，顶层模块(Verilog source code for serial communication under vivado 2017.4, which transmits 8 bits at a time, including sending module, receiving module and top module)
- 2020-06-22 20:20:01下载
- 积分：1
-
asynchronous-fifo
同步fifo的调用程序，调用Quartus II 9.0 (32-Bit)中的fifo模块(Synchronous fifo calling program, call Quartus II 9.0 (32-Bit) in fifo module)
- 2013-08-23 21:58:56下载
- 积分：1
-
基于fpga的计算器
资源描述基于fpga的一个简易计算器程序，能够通过开发板输入，并且通过开发板数码管显示出来
- 2023-08-27 21:45:03下载
- 积分：1
-
指令Cache的verilog代码
16位cpu的icache verilog实现代码，每行4个字，并且通过字节寻址，映射方式为直接映射，使用查表法。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。
- 2022-11-02 18:00:03下载
- 积分：1
-
RISC
32 bit RISC Processor with 3 stage pipeline
- 2010-03-03 00:09:16下载
- 积分：1
-
uart01
一种实现计算机接口rs232与FPGA通信的基于VHDL语言设计的一段非常简洁的程序(A RS232 computer interface implementation with FPGA-based VHDL language communications designed a very simple procedure)
- 2009-03-15 23:13:42下载
- 积分：1
-
keyscan
用verilog语言写的简单的键盘扫描代码，适合初学者，用alter的软件编写的程序代码。(Using verilog language to write simple keyboard scan code, suitable for beginners, with alter software program written code.)
- 2013-09-13 22:59:11下载
- 积分：1
-
code
Due to its high modularity and carry-free addition, a redundant
binary (RB) representation can be used when designing high performance
multipliers. The conventional RB multiplier requires an additional RB partial
product (RBPP) row, because an error-correcting word (ECW) is generated
by both the radix-4 Modified Booth encoding (MBE) and the RB encoding.
This incurs in an additional RBPP accumulation stage for the MBE multiplier.
In this paper, a new RB modified partial product generator (RBMPPG) is
proposed; it removes the extra ECW and hence, it saves one RBPP
accumulation stage.
- 2017-10-01 23:34:56下载
- 积分：1
-
leading-zero
对于32位寄存器前导零个数的计数，一个简单的程序(32 registers a leading zero number of counts, a simple procedure)
- 2012-06-05 16:41:11下载
- 积分：1
-
digital_clock
数字钟通过verilog实现，并且支持Modelsim仿真，通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分：1
