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password
verilog代码实现的数字密码锁。通过4个并行的10位移位寄存器，分别记录在时钟上升沿时A,B,C,D的输入情况，比如某上升沿输入A，相应时刻A对应的移位寄存器输入1，其他三个移位寄存器输入都为0.另外4个并行的10位寄存器记录密码。这样，密码锁不仅可以识别字符数量，还可以判断出字符的输入次序。(verilog code of digital lock. By four parallel 10-bit shift register, respectively, recorded in the clock rising edge A, B, C, D of inputs, such as a rising edge of input A, the corresponding moments A 1 corresponding to the input shift register, the other three shift bit register inputs are 0. another four parallel 10-bit registers record the password. This lock can not only identify the number of characters, you can also determine the character of the input sequence.)
- 2011-10-18 21:45:45下载
- 积分：1
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MCU_V_PWM_16bit
单片机通过总线，将占空比和频率送到CPLD/FPGA中，并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)
- 2020-10-29 09:19:57下载
- 积分：1
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BT1120转GTX详细设计方案
bt1120设计方案，描述了具体的方案设计以及整体的架构设计(Bt1120 design scheme, describes the specific scheme design and the overall architectural design)
- 2020-06-25 05:40:02下载
- 积分：1
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03_hbf_test_128m22
说明： 半带滤波器，工作在采样率122.88Msps上(Half-band filter, working at the sampling rate of 122.88 Msps)
- 2020-12-23 10:59:07下载
- 积分：1
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maichongceliang
对于已获得的脉冲包络采样序列，需测量的脉冲特征参数主要有：脉冲幅值(PA)、脉冲到达时间(TOA)和脉冲宽度(PW)。实际测量中，脉冲波形的形状是各种各样的，但其主要的参数有脉冲幅度、脉冲宽度、脉冲周期、脉冲占空比、脉冲前沿(上升时间)、脉冲后沿(下降时间)、脉冲上冲、脉冲下冲、脉冲下垂、脉冲顶部不平度等，脉冲参数的计量主要就是对这些参数进行计量。本程序包实现基于FPGA实现脉冲宽度和重复周期的测量。(Who have access to the pulse envelope sample sequence, the pulse measurement to be the main characteristic parameters are: pulse amplitude (PA), pulse time of arrival (TOA) and pulse width (PW). The actual measurement, the pulse shape is a wide variety of shapes, but its main parameters of the pulse amplitude, pulse width, pulse period, pulse duty cycle, pulse leading edge (rise time), pulse along (down time), the red pulse, pulse undershoot, pulse droop, pulse irregularities, such as at the top, the measurement of pulse parameters is mainly the measurement of these parameters. The package FPGA-based pulse width and repetition to achieve the measurement cycle.)
- 2009-07-08 14:32:08下载
- 积分：1
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设计和ASIC平台实现DDR SDRAM控制器
专用的内存控制器是素数在不包含的微处理器的应用程序的重要性（高端应用）。内存控制器提供内存刷新指令信号，读取和写入操作和SDRAM的初始化。我们的工作将集中于ASIC双数据速率（DDR）SDRAM设计方法控制器位于DDR SDRAM和总线之间高手。控制器简化了SDRAM命令接口标准的系统的读/写接口，也优化的读/写周期的存取时间。双倍数据速率（DDR）SDRAM控制器使用Cadence RTL实现编译器。
- 2023-02-20 15:00:04下载
- 积分：1
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9536
Xilinx user constraints file for the cpld xc9536 or xc9536xl or xc9572 or xc9572xl
- 2012-11-06 11:49:12下载
- 积分：1
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DE2_115_CAMERA
d5m的DE2驱动Verilog HDL (d5m driven on DE2 by Verilog HDL )
- 2020-07-09 20:38:55下载
- 积分：1
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bayer2rgb
bayer to rgb,
module Bayer2RGB(
input MainClk,
input nRST,
input iVsync,
input iHref,
input[9:0] iPixelData,
&nbs
- 2022-08-17 06:48:57下载
- 积分：1
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FXY
说明： FPGA做波形发生器，产生8种波形，包括三角波，正弦波，锯齿波，方波等。(FPGA is used as waveform generator,Generate 8 waveforms, including triangle, sine, sawtooth, square, etc.)
- 2019-07-16 16:01:45下载
- 积分：1
