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reed_solom
REEDSOLOMON source code
- 2010-04-30 17:44:52下载
- 积分:1
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FFT_16
FFT快速傅立叶变换-verilog,基于verilog的FFT源码,QuartusII上仿真通过(FFT Fast Fourier Transform-verilog, the FFT-based verilog source, QuartusII through the simulation)
- 2020-09-08 20:28:02下载
- 积分:1
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fftip
2008-2009年优秀硕士论文之:基于FPGA的高性能32位浮点FFT IP核的开发(Outstanding Master' s thesis 2008-2009: FPGA-based high-performance 32-bit floating-point FFT IP core development)
- 2010-12-09 19:31:46下载
- 积分:1
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移位相加乘法器
应用背景此代码是移行为模型和添加乘数随着乘数和被乘数参数比特宽度关键技术Verilog 2001和Xilinx的Spartan 6 FPGA板试验台
- 2022-08-13 06:56:10下载
- 积分:1
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counter
说明: 基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)
- 2020-06-20 21:00:01下载
- 积分:1
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Tym605V2Demo
FPGA(赛灵思)试验箱 实验程序 有Audio,Buzzer,key,ledarray,ledseg.......(FPGA(赛灵思)试验箱 实验程序Audio,Buzzer,key,ledarray,ledseg)
- 2012-02-11 21:09:19下载
- 积分:1
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IC设计基础
说明: 一本很经典的IC设计中文入门书籍,由任艳颖,王彬编著,翻印几百万册(A very classic introduction to Chinese in IC design book, compiled by Ren Yanying and Wang Bin, reprinted millions of copies)
- 2020-06-23 22:20:02下载
- 积分:1
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CRC _ Verilog 16
vivado工程下的Verilog语言的CRC_16,并行输入任意字节长度,均可求出来,数据的校验码,代码给的是512个字节宽度的数据源,长度可以自行修改,亲测实际工程~~~
- 2022-01-29 03:28:35下载
- 积分:1
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16 位进行选择加法器 verlog 代码
它是为使用多个波纹的常规结构的 16 位进行选择加法器 verilog 代码执行加法器和多路复用器
- 2022-09-08 16:00:02下载
- 积分:1
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802-11-Frame_E_C
Frame Control field
Retry:
Set in case of retransmission frame
More fragments:
Set when frame is followed by other fragment
Power Management
bit set when station go Power Save mode (PS)
More Data:
When set means that AP have more buffered data for a
station in Power Save mode
- 2016-08-23 17:37:40下载
- 积分:1