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Random_Derandom
通信中加扰/解扰算法。FPGA源代码,verilogHDL语言实现,包含测试程序。(Perturbation/perturbation algorithm. FPGA source code, verilogHDL language implementation, including test procedures.)
- 2020-08-12 13:38:27下载
- 积分:1
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2通道ADC Ads527x的采集实现Vhdl
2通道模数转换器的采集实现。包含VIRTEX-II
和SPARTAN-III
两种类型的FPGA元件,模数转换器件为ADS527X系列,含仿真代码。采用VHDL语音实现,具有参考价值。
- 2022-01-20 23:16:05下载
- 积分:1
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verilogsram
SRAM 读写实验,SRAM存储器的读写操作,Verilog源码有助于提高代码coding能力。使用例程。(SRAM write and read)
- 2017-04-20 22:20:05下载
- 积分:1
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VerilogHdlPracticeAndSystemDesign
本RAR包括《Verilog-HDL实践与应用系统设计》一书中的全部例子,这些例子全部通过了验证。第七章以后的设计实例,不仅有Verilog-HDL的例子,也附了包括VB、VC++等源程序,甚至将DLL的生成方法也详尽地作了说明。(The RAR includes " Verilog-HDL Practice and Application of system design," a book full of examples, all passed validation. Chapter VII of the future design examples, not only examples of Verilog-HDL, but also attached, including VB, VC++ source code, etc., and even DLL generation methods explained in detail.)
- 2009-11-10 19:40:12下载
- 积分:1
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xds100v3r2.0
TI DSP XDS100V3仿真器原理图Rev2.0(TI DSP XDS100V3 schematic Rev2.0)
- 2013-01-27 00:44:06下载
- 积分:1
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GPU_LDPC+硕士毕设论文详解
QC LDPC的编码译码 代码与论文配套 是研究生毕设 可运行 代码风格优秀(QC LDPC Coding and Decoding Code and Paper Matching are Excellent Style of Running Code for Graduate Students)
- 2021-05-14 19:30:07下载
- 积分:1
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四位除法器的VHDL源程序
四位除法器的VHDL源程序-four division of VHDL source
- 2022-01-27 20:04:11下载
- 积分:1
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Verilog-shift-mulfunction
FPGA verilog 实现任意位宽的移位相乘法,有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
)
- 2014-06-21 17:08:12下载
- 积分:1
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32位元浮点数加法器,用于以VHDL编写的32位元CPU
32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
- 2022-10-08 15:20:02下载
- 积分:1
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serial port simulated programme of lattice
lattice的串口仿真的程序- serial port simulated programme of lattice
- 2023-04-29 09:40:03下载
- 积分:1