登录
首页 » Verilog » 编码的 booth 型乘法器

编码的 booth 型乘法器

于 2023-06-18 发布 文件大小:1.37 kB
0 81
下载积分: 2 下载次数: 1

代码说明:

这是编码的 booth 型乘法器。输入具有 32 位和输出是 64 位。您可以使用 is_signed 信号来确定符号和无符号的输入和输出 !

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • Add_sub_struc
    8位加减器,八位减法器与加法器,用过一个控制端可以自由变换,采用移位加法方式,用途广泛,利用减法位补码加法的理论实现。(8 addition and subtraction, eight subtractor and adder, used a control terminal can freely change the using Shift addition, a wide range of uses, the use of subtraction complement addition theory to achieve.)
    2012-05-14 20:36:26下载
    积分:1
  • ppmencoder
    一个八位的并行输入,串行输出的编码器;带有开头结尾帧。(It is an encode with eight palallel input and a serial output.)
    2020-11-23 01:19:34下载
    积分:1
  • FPGA_UART
    用Verilog语言实现的FPGA UART独立收发模块 思路简单,代码简洁。在Lattice LFE3EA VERSA开发板上验证通过,编译器Lattice Diamond. 功能:串口收到数据后立即回传,此后每一秒串口数据+1再发送。(Using Verilog language independent of FPGA UART transceiver idea is simple, concise code. Development board in Lattice LFE3EA VERSA verified by the compiler Lattice Diamond. Features: Serial data is received immediately after the return, then every second serial port and then send the data+ 1.)
    2011-10-03 13:18:56下载
    积分:1
  • Continuous_delay_control_Farrow
    matlab代码,利用Farrow结构设计分数延时滤波器,滤波器阶数和个数可分别进行设置,利用最大最小准则近似(Matlab code, using Farrow structure design fractional delay filter, filter order and number can be set separately, using the maximum and minimum criterion approximation.)
    2019-06-14 09:10:59下载
    积分:1
  • chengxu
    设计制作一个可容纳4组参赛者的数字智力抢答器,每组设置一个抢答按键; 电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后,若参加者按抢答键,则该组指示灯亮并用组别显示抢答者的组别。此时,电路具有自锁功能,使别组的抢答开关不起作用。 设置计分电路。每组在开始时预置成6分,抢答后主持人计分,答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
    2012-06-10 12:58:44下载
    积分:1
  • cordic
    基于VHDL语言编写,可下载到FPGA板子上实现的cordic算法实现的设计,并用该算法实现sin和cos的计算,计算结果显示在数码显示管上,已包含按键防抖动功能的实现。(Based on VHDL language, can be downloaded to the the cordic algorithm implemented in the FPGA board to achieve the design and calculation of sin and cos using this algorithm, the results displayed on the digital display tube is included on the function of the realization of the button shake.)
    2013-03-21 16:52:41下载
    积分:1
  • decodeLogDomainSimple
    When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.
    2017-01-29 18:04:53下载
    积分:1
  • FFT
    很好的fft学习程序感兴趣的同学可以看哈,下载一下。(it is very good )
    2012-04-04 16:00:42下载
    积分:1
  • Verilog 汽车尾灯
    汽车尾灯控制 能够实现 直行 左转 右转 左转刹车 右转刹车 直行刹车 故障等情况下的车灯控制 汽车尾灯控制 能够实现 直行 左转 右转 左转刹车 右转刹车 直行刹车 故障等情况下的车灯控制
    2022-05-17 08:27:12下载
    积分:1
  • FPGA基于PCIE的DMA测试
    利用ISE工具,完成对v6系列的FPGA上PCIE以及DMA数据测试仿真,可以通过编译产生仿真波形,也可以根据自己的开发板烧录到自己的板子上
    2023-08-18 13:05:05下载
    积分:1
  • 696518资源总数
  • 105949会员总数
  • 22今日下载