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source_file
说明： 有限状态机 rtl code 和 TB验证环境(Finite state machine RTL code and TB verification environment)
- 2020-08-13 15:05:19下载
- 积分：1
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AD7606URAT
Verilog实现高速AD7606数据采样，8通道，采样频率可调，支持串口数据发送，亲测可用。(Verilog AD7606 high-speed data sampling, 8-channel, the sampling frequency is adjustable, support for serial data transmission, pro-test is available.)
- 2021-04-16 21:38:53下载
- 积分：1
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yibuqingling
含异步清零和同步清零的计数器的设计，内容是源代码，以及相关文件，打开即可(Clear cleared asynchronous and synchronous with the counter design, content source code and related documents, can be opened)
- 2011-08-24 10:44:33下载
- 积分：1
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SDRAM
基于fpga与verilog语言的的sdram读写(SDRAM reading and writing based on FPGA and Verilog language)
- 2018-01-16 11:24:03下载
- 积分：1
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line_four
利用verilog HDL逐点比较法实现直线和圆弧插补(Use verilog HDL by-point comparison method to achieve linear and circular interpolation)
- 2020-12-01 14:59:27下载
- 积分：1
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TLC5510
TLC5510的驱动程序，采用Verilog语言编写(TLC5510 driver, the use of Verilog language)
- 2020-08-13 21:38:29下载
- 积分：1
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Escalimetro
all funtions for a scale meter for maps in a 8051 microcontroler with an alphanumeric lcd display
- 2012-12-25 02:14:17下载
- 积分：1
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LMS算法FPGA仿真
说明： 自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分：1
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Serial_Adder
注意：是verilog语言写的
一bit的全加器，实现4位数的串行加法器，一个时钟能完成一次一bit的全加(Note: It is verilog language to write a bit full adder, to achieve four-digit serial adder, a clock can be completed once a bit full adder)
- 2020-10-30 20:09:55下载
- 积分：1
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pipeline_booth_mult_16
用流水线的方法实现16位乘法器，运算速度快，消耗时钟资源少(Pipeline method to realize 16-bit multiplier, which is fast in operation and consumes less clock resources)
- 2020-09-29 18:17:44下载
- 积分：1
