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USB1.1 IP核心控制设备,用硬件描述语言…
usb1.1的设备控制器IP核,是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
- 2022-01-30 21:54:55下载
- 积分:1
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ram_2
简易双口ram,使用两个ram ip core,一个写的同时另一个读,并且包含按键使能和数码管以及流水灯显示(Simple dual-port ram, two ram the ip core, a write while another read, and contains buttons to enable digital pipe and the water light show)
- 2012-07-08 13:05:27下载
- 积分:1
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square_syn
说明: 平方环载波同步法FPGA实现的verilog代码(square loop carrier wave syn)
- 2021-03-04 23:59:32下载
- 积分:1
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FPGA和DSP EMIFA口接口程序。在两FPGA分布
FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.-FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
- 2023-01-25 08:30:04下载
- 积分:1
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基于fpga的DDS程序 AD9767
基于fpga的DDS程序 可输出正弦波 方波 三角波 锯齿波(DDS program based on FPGA can output sinusoidal square wave triangular wave sawtooth wave)
- 2020-06-20 21:00:01下载
- 积分:1
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xilinx原语的使用方法
说明: Xilinx原语的使用介绍,特别全面,希望对大家有所帮助,(Introduction to the use of Xilinx primitives, particularly comprehensive,I hope it will be helpful to you all.)
- 2019-04-16 22:50:07下载
- 积分:1
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myconstellation_final_2
bpsk qpsk 16qam 64qam的constellation(bpsk qpsk 16qam 64qam constellation)
- 2021-03-03 01:49:33下载
- 积分:1
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一种RISC结构8位微控制器的设计与实现
一种RISC结构8位微控制器的设计与实现-The structure of a RISC micro-controller" s 8 Design and Implementation
- 2023-08-07 22:10:06下载
- 积分:1
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UART_CESHI
基于VHDL语言的串口发送和接收程序,自己调试通过,并已经运用在工程中(Based on the serial port to send and receive procedures VHDL language, its own debugging, and has been used in the project)
- 2016-08-05 15:27:54下载
- 积分:1
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FSK
FPGA实现FSK调制,带Modelsim仿真,实际系统测试通过,载波信号,信号频率等可调。(FPGA implementation FSK modulation with Modelsim simulation, the actual system test, the carrier signal, the signal frequency is adjustable.)
- 2020-09-03 11:38:07下载
- 积分:1