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clock
软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分:1
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FPGA_MVB
此论文想详细阐明了用FPGA做硬件处理,集成SOPC功能实现MVB通讯协议的解决方案,可以运行在alter fpga上面。(This paper expounds in detail the processing to do with FPGA hardware, integrated solutions for SOPC function of the realization of MVB communication protocol, can run in alter FPGA above.)
- 2021-01-03 17:58:56下载
- 积分:1
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alu
this is the vhdl code for the arithmetic logic unit.enjoy!
- 2013-08-22 18:51:35下载
- 积分:1
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一个高级培训班的内部资料,非常宝贵,读者可以掌握FPGA的基本思路
一个高级培训班的内部资料,非常宝贵,读者可以掌握FPGA的基本思路-A high-level training of internal information, are very valuable, readers can grasp the basic ideas FPGA
- 2022-03-13 01:35:04下载
- 积分:1
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400rdm
用于FPGA的学习,大家值得借鉴,可以好好学习一下(this is for fpga and you can use this.)
- 2020-06-16 15:20:02下载
- 积分:1
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I2C Bus Controller ALTERA the VHDL source code
I2C总线控制器 altera提供的VHDL的源程序代码-I2C Bus Controller ALTERA the VHDL source code
- 2022-01-25 15:11:56下载
- 积分:1
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rough22
采用倍频及1/3、1/12倍频绘制的路面不平度频谱图(自编)(Using octave and 1/3, 1/12 octave drawn road roughness spectrum (self))
- 2013-09-10 16:50:13下载
- 积分:1
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Nut
UG二次开发,课程作业,研究生,学习,初学者,打孔,复杂体,阵列
UG C program,homework,student,study,first,hole,complex,many(
UG C program,homework,student,study,first,hole,complex,many)
- 2015-01-15 12:26:29下载
- 积分:1
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e1framer
E1 deframmer and Frammer.
- 2013-02-25 19:43:35下载
- 积分:1
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vhdl 中各种数据类型的转换实现,可以调用函数库实现
vhdl 中各种数据类型的转换实现,可以调用函数库实现-date type change
- 2022-03-18 06:02:30下载
- 积分:1