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完成ITUR656标准的视频流数据向RGB格式的转换。
完成ITUR656标准的视频流数据向RGB格式的转换。-Complete video streaming ITUR656 standard data format to RGB conversion. Test module
- 2022-02-13 16:12:20下载
- 积分：1
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1、ps/2键盘输入，通过led显示ascii码
2、稍等1s可以在lcd上显示输入的字符
3、其中键盘上的backspce键是用来清屏的
4、当l...
1、ps/2键盘输入，通过led显示ascii码
2、稍等1s可以在lcd上显示输入的字符
3、其中键盘上的backspce键是用来清屏的
4、当lcd上显示满字符时，在按下按键自动清屏，从第一行显示。-1, ps/2 keyboard input, through the led display ascii code 2, wait 1s in the lcd display characters input 3, which backspce keys on the keyboard was required to settle the screen 4, when the lcd display full of characters, the press the button automatically Qing-ping, from the first line of display.
- 2022-01-31 12:27:49下载
- 积分：1
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ASIC_LIB
ASIC设计中常用的运算模块，如加减，常系数乘法，截断，饱和等。(some modules used in ASIC design.)
- 2010-03-10 15:52:28下载
- 积分：1
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ldpc_decoder_802_3an
802.3an ldpc码编码、译码设计，使用VERILOG hdl语言编写，包括测试代码，(802.3an ldpc code encoding, decoding the design, use of language VERILOG hdl, including test code,)
- 2021-02-14 15:29:49下载
- 积分：1
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tAtan2Cordic
是codic算法实现atan的C程序，包括定点和浮点程序，已经通过验证。(Atan is codic algorithm of C procedures, including fixed-point and floating-point procedures, has been validated.)
- 2021-02-04 09:59:58下载
- 积分：1
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oc i2c master
NIOSII I2C接口模块及驱动程序，并含有测试程序。对想开发NIOS的工程师很有帮助(NIOSII I2C interface module and driver, and contains the test procedures. NIOS of engineers want to develop useful)
- 2007-08-20 19:37:02下载
- 积分：1
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algorithm_design_and_logic_implemention
本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础(This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog)
- 2009-11-11 21:19:03下载
- 积分：1
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Block-Landscape-Design
3D的效果，逼真的视觉享受，真实的场景。(3D effects, realistic visual experience, the real scene.)
- 2014-06-10 19:28:29下载
- 积分：1
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The experimental results are used to prepare MOSIN6 is achieved Verilog HDL lang...
有实验结果,用MOSIN6编写的,是Verilog HDL语言实现的.
练习三 利用条件语句实现计数分频时序电路
实验目的：
1. 掌握条件语句在简单时序模块设计中的使用；
2. 学习在Verilog模块中应用计数器；
3. 学习测试模块的编写、综合和不同层次的仿真。
练习四 阻塞赋值与非阻塞赋值的区别
实验目的：
1． 通过实验，掌握阻塞赋值与非阻塞赋值的概念和区别；
2． 了解阻塞赋值与非阻塞赋值的不同使用场合；
3． 学习测试模块的编写、综合和不同层次的仿真。
-The experimental results are used to prepare MOSIN6 is achieved Verilog HDL language. Practice the use of conditional statements to achieve the three sub-frequency timing circuit count experimental purposes: 1. Have conditional statements in the simple timing of the use of modular design 2. Learning modules in the Verilog Application of counter 3. to learn the preparation of the test module, integrated and different levels of simulation. Practicing the four blocking assignment with the distinction between non-blocking assignment experimental purposes: 1. Through experiments, hands blocking assignment with the concept of non-blocking assignment and distinction 2. Understanding of blocking and nonblocking assignment assignment usi
- 2022-03-18 15:26:04下载
- 积分：1
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LVDS_RX
说明： lvds_rx IP核硬件设计代码，使用时注意LVSD_RX模块的延时参数的设置，3.5倍时钟相位的设置(Lvds IP core hardware design code, when using the attention LVSD module delay parameter settings, 3.5 times the clock phase settings)
- 2021-04-26 11:38:45下载
- 积分：1
