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i2c
说明: 本文研究的IIC总线控制器具有如下特征
1.兼容飞利浦I2C标准,以主机模式与外围设备进行数据通信,对IIC从机模型进行读/读,读/写,写/写,写/读[18]。
2.多主操作
3.软件可编程时钟频率
4.时钟拉伸和等待状态生成
5.软件可编程确认位
6.时钟同步设计
7.仲裁中断丢失,自动转移取消
8.开始/停止/重复启动检测/确认生成
9.总线忙检测(The IIC bus controller studied in this paper has the following characteristics.
1. Compatible with Philips I2C standard, data communication between host mode and peripheral devices, read/read, read/write, write/write, write/read for IIC slave model [18].
2. Multiple Main Operations
3. Software programmable clock frequency
4. Clock stretching and waiting state generation
5. Software Programmable Confirmation Bit
6. Clock Synchronization Design
7. Loss of arbitration interruption and cancellation of automatic transfer
8. Start/Stop/Repeat Start Detection/Verification Generation
9. Bus busy detection)
- 2019-06-18 12:18:10下载
- 积分:1
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IIC-SOPC
SOPC系统的I2C代码 直接可用,可作为IP核用到自己的系统中(SOPC system I2C code directly available, can be used as an IP core in your system)
- 2010-10-22 09:51:13下载
- 积分:1
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pn_gen_vhd_211
通信中常用的PN序列产生器的源代码全部打包(Communications commonly used in PN sequence generator, the source code of all packaged)
- 2009-02-04 15:41:17下载
- 积分:1
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12_lcd12864
本实验是用LCD12864显示英文
显示
Our FPGA EDA
NIOS II
SOPC
FPGA(This experiment is shown in English with LCD12864 display Our FPGA EDA NIOS II SOPC FPGA)
- 2013-06-26 11:35:54下载
- 积分:1
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VHDL实现led灯的动态扫描,主要对CLK进行分频
VHDL实现led灯的动态扫描,主要对CLK进行分频-VHDL realization led lamp dynamic scan, the main points of the CLK to the frequency
- 2023-03-21 08:35:04下载
- 积分:1
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uart
使用FPGA实现UART收发。支持多种波特率。(Using FPGA to achieve UART transceiver.)
- 2020-11-07 15:29:50下载
- 积分:1
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LMS算法FPGA仿真
说明: 自适应滤波器算法LMS ,的FPGA实现,采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分:1
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VHDL USB2.0接口源码,内有说明,详细.
VHDL USB2.0接口源码,内有说明,详细.-VHDL USB2.0 interface source code, which is described in detail.
- 2022-04-29 19:53:42下载
- 积分:1
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jisuanqishijianxianshi
基于FPGA编写一个时间显示,计数功能,年月显示的程序,(FPGA-based preparation of a time display, counting, years show program,)
- 2011-08-30 16:00:48下载
- 积分:1
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异步串行接口电路及数据传输模块设计
设计要求1) 每帧数据供 10 位,其中 1位启动, 8位数据, 1位 停止。2) 波特率为: 9600 。3) 收发误码率
- 2023-09-07 19:10:03下载
- 积分:1