-
基于单片机与CPLD的 等精度频率计,VHDL语言
基于单片机与CPLD的 等精度频率计,VHDL语言-Based on SCM and CPLD
- 2022-11-25 20:35:03下载
- 积分:1
-
Desktop4
combinational circuits code in vhdl
- 2018-08-13 17:33:14下载
- 积分:1
-
FPGA
用Vrilog产生一个混沌信号,并用MATLAB仿真,画出波形。(With Vrilog generate a chaotic signal simulation using MATLAB, draw the waveform.)
- 2012-11-15 20:29:35下载
- 积分:1
-
AD9777_SPI_CONFIG
verilog ad9777 ad芯片的配置程序,SPI接口协议 16bit DA(Verilog ad9777 AD chip configuration program, SPI interface protocols for 16 bit DA)
- 2020-07-29 21:08:38下载
- 积分:1
-
VHDL出租车计费代码
该代码实现出租车计费功能,例如起步价为5元,按住相关控件后,每隔五秒,计数将加1,实现类似于开车时计费的功能,当松开按键后,计费也将停止。。。。
- 2022-02-14 00:52:30下载
- 积分:1
-
counter
基于fpga的计数器模块 分频 可移植 完美实现(Perfect realization of frequency division and portability of counter module based on FPGA)
- 2020-06-20 21:00:01下载
- 积分:1
-
线性反馈移位寄存器的随机数发生器
线性反馈移位寄存器的最右侧位称为输出位。水龙头是 XOR 按顺序和输出位,然后反馈到最左边的位。在最右边的位置的位序列的叫做输出流。双边投资条约中的线性反馈移位寄存器状态影响输入被称为水龙头 (在图中的白色)
- 2022-02-13 22:21:05下载
- 积分:1
-
SD卡上有音频部分!希望对大家有用!
有关于SD卡的音频部分!希望对大家有用!-SD cards have on the audio portion! Hope useful for everyone!
- 2022-02-05 13:29:26下载
- 积分:1
-
123456shouhuoji
售货机-VHDL语言-已调试通过
真的很好用哦~适合一切学习EDA的初学者,能够让你轻松度过EDA课!~(Vending machine-VHDL language- has been really good with debugging by Oh ~ EDA for all beginners to learn, to let you easily through the EDA class! ~)
- 2010-05-09 22:31:14下载
- 积分:1
-
基于FPGA的OFDM信号传输系统VHDL源码
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
- 2022-02-13 14:58:13下载
- 积分:1