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verilog_422
标准RS422 Verilog源代码， 传输波特率可以修改， FPGA上可以工作(Standard RS422 verilog communication source code, buardrate can be updated and it is fully work in FPGA )
- 2021-04-06 14:29:02下载
- 积分：1
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axi_spi_master
arm的axi接口转spi接口master源代码，已经使用过，带注释，
- 2022-03-23 04:14:36下载
- 积分：1
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uart
it contains pdf file which has vhdl program of uart (universal asynchoronus receiver and transmitter). which very simple and easy to understand
- 2010-04-22 20:47:55下载
- 积分：1
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LS-versus-MMSE
这是基于MIMO-OFDM的同步算法研究的源程序。本程序采用的极大似然估计的方法。(This is based on MIMO-OFDM synchronization algorithm source code. The program uses the method of maximum likelihood estimates.
)
- 2012-12-13 15:32:49下载
- 积分：1
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pinlvji
频率计
测量范围1-100MHz
测量阈值0.1s
计数部分为FPGA/CPLD
语言VHDL
显示部分为51
单片机加八位数码管
语言C(Frequency meter
Measuring range 1-100 MHZ
Measure threshold is 0.1 s
Count part of FPGA/CPLD
Language VHDL
Display part of 51
MCU with eight digital tube
Language C)
- 2020-10-30 20:39:55下载
- 积分：1
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DE2_115_TV
这个代码主要实现了基于VHDL的关于TV方面的功能。(This code is the main achievement of the VHDL about aspects of the function based on TV.)
- 2013-03-06 21:49:22下载
- 积分：1
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RIPPLE_COUNTER
Ripple counter using t _filp flop
- 2017-11-16 05:22:36下载
- 积分：1
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wireless
基于FPGA DE0以及niosII的射频无线发送程序,采用spi接口操作无线模块nrf24l01(To spi interface operation wireless module nrf24l01 of FPGA DE0, as well niosII RF wireless transmitter program)
- 2012-12-02 22:46:14下载
- 积分：1
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example
一个电子秒表，最大显示59.99,具有暂停和reset功能(An electronic stopwatch, the maximum display 59.99, with a pause and reset functions)
- 2013-12-17 12:28:14下载
- 积分：1
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spi-MRAM
Everspin SPI MRAM chipset(MR25H10,MR25H40,MR25H256)
- 2013-08-14 12:05:26下载
- 积分：1
