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8.4-ADC0809-VHDL-control-program
基于VHDL语言，实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)
- 2011-11-29 08:43:07下载
- 积分：1
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Send-Program
program send sms by sim900 module
- 2012-08-08 18:25:11下载
- 积分：1
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sobel
Verilog代码实现Sobel算子，包括整个工程，仿真也有。。仿真表明该程序能实现Sobel 算子硬件实现(Verilog，Sobel Operator)
- 2011-05-10 21:11:21下载
- 积分：1
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simwindfarm-v1.0
GFHGFHGFH DFHFDHD GHDHFDHHFD DFHFDHDF
- 2021-04-11 22:08:57下载
- 积分：1
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模拟Sim的简单代码
module example_3_1(A, B, C, D, E);
output D, E;
input A, B, C;
wire w1;
and G1(w1, A, B);
not G2(E, C);
or G3(D, w1, E);
endmodule
- 2022-10-09 10:35:03下载
- 积分：1
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SystemOfTaxiFeeBasedOnVerilogHDL
摘 要：以上海地区的出租车计费器为例，利用Verilog HDL语言设计了出租车计费器，使其具有时间
显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示
了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。源程序经MAX+PLUS Ⅱ软件调试、优
化，下载到EPF1OK10TC144—3芯片中，可应用于实际的出租车收费系统。
关键词：Verilog HDL；电子自动化设计；硬件描述语言；MAX+PLUSⅡ(Abstract: Shanghai taxi meter as an example, the use of Verilog HDL language designed taxi meter so that it will have the time display, billing, as well as analog taxis to start, stop, reset and other functions, and set up a dynamic scanning circuit shows that the fare and the corresponding time, shows the hardware description language Verilog-HDL design of the superiority of digital logic circuits. Source by MAX+ PLUS Ⅱ software debugging, optimization, downloaded to EPF1OK10TC144-3 chip, can be applied to the actual taxi fare collection system. Keywords: Verilog HDL electronic design automation hardware description language MAX+ PLUS Ⅱ)
- 2007-09-11 10:52:52下载
- 积分：1
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dw_apb_rtc_db
verilog实现rtc文档，可用于实现RTC。(verilog realize rtc document can be used to implement the RTC.)
- 2016-04-05 22:39:37下载
- 积分：1
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Roy dsd
basic verilog code on siso, piso, sipo
- 2020-06-25 18:40:01下载
- 积分：1
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electrical lock
一个用Verilog写的电子锁工程，带testbench。(An electronic lock project written in Verilog with testbench.)
- 2020-06-30 05:00:01下载
- 积分：1
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VHDL
FPGA 12864显示程序 VHDL程序！！(FPGA 12864 show program
)
- 2012-05-30 22:09:54下载
- 积分：1
