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i2s_input
基于FPGA的i2s接口输入模块设计，其中有原理图和verilog源码，可在Quartus环境下进行仿真(FPGA-based i2s interface input module design, including schematics and verilog source code, can be simulated in Quartus environment)
- 2020-12-14 16:49:14下载
- 积分：1
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Buffer-DAQ
基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)
- 2015-01-11 19:09:49下载
- 积分：1
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vga_driver
verilog语言设计的VGA驱动。在Quarus11.0下编译成功，并在Altera cyclone4开发板上测试OK(verilog language design VGA driver. In Quartus11.0 successfully compiled and Altera cyclone4 development board test OK)
- 2016-05-25 17:19:18下载
- 积分：1
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N-bits-by-M-bits
这是一个verilog代码实现的常用乘法器。设计的是通用N比特乘M比特的二进制乘法器(This is a common multiplier verilog code. Design of a generic N bits by M bits of the binary multiplier)
- 2013-10-05 19:44:52下载
- 积分：1
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用verilog写的cpld的各种分频程序，希望大家指正，谢谢！
用verilog写的cpld的各种分频程序，希望大家指正，谢谢！-using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
- 2023-01-20 06:35:04下载
- 积分：1
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subway-ticket-vending-system
本设计是基于FPGA设计一个地铁自动售票系统。 本设计采用自顶向下的模块化设计方法，基于FPGA使用VHDL语言设计制作一个地铁自动售票控制系统，该系统能出售2条线路3种不同价位的票，完成售票、找零、显示等功能。(The design is based FPGA design of a subway ticket vending system. This design uses a top-down, modular design method, a subway ticket vending control system based on FPGA using VHDL language design, the system can sell two lines of different priced tickets, complete the ticket, give change, display and other functions .)
- 2013-02-27 12:59:49下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
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DESHTM
用VHDL语言实现了DES加密算法，其中包含了测试程序，能够进行仿真。(Using VHDL language implementation of the DES encryption algorithm, which contains the test procedures can be simulated.)
- 2009-03-15 12:29:56下载
- 积分：1
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I2C主/从
用vhdl编写的主从式代码，会比较接近，它涉及i2c接口，主从式，每行都有注释，我建议如果你想对代码进行编辑就使用灵活的编辑器
- 2022-04-01 17:07:54下载
- 积分：1
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USB_xilinx_vhdl
说明： Giao tiep Univesan ...
- 2020-06-20 03:00:02下载
- 积分：1
