-
Verilog_code_for_AWGN
说明： verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。(verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence. )
- 2021-01-14 16:48:47下载
- 积分：1
-
乐曲演奏电路，可以播放歌曲在数码管上显示相同的时间…
乐曲演奏电路，能演奏歌曲，同时在数码管上显示演奏的乐曲音符的数字。-Music concert circuit, can play songs at the same time in the digital tube displays the number of notes played music.
- 2023-01-23 08:45:03下载
- 积分：1
-
digital-processing-with-FPGA
vhdl语言，国外教材，数字信号处理算法(vhdl language, foreign materials, digital signal processing algorithms)
- 2016-07-22 21:53:49下载
- 积分：1
-
OQPSK
说明： 这是一个关于dQPSK的Matlab程序
这是一个关于dQPSK的Matlab程序 (This is a dQPSK the Matlab program This is a dQPSK the Matlab program)
- 2010-04-21 12:46:25下载
- 积分：1
-
generate-coordinates
使用VHDL编写语言，巧妙的利用计数器和循环输出一个坐标系，由于VHDL出现负数比较麻烦，全部由正数代替，输出一个原点在中心，半径128的256×256的坐标。方便坐标变换以及用此坐标做算法。(Use of VHDL language, clever use of counter and loop outputs a coordinate system, because VHDL negative too much trouble, all replaced by a positive number, the output an origin at the center, radius 128 256 256 coordinates. Convenient coordinate transformation and coordinate to do with this algorithm.)
- 2013-08-28 11:03:46下载
- 积分：1
-
weitb
在数字通信中，通常直接从接收到的数字信号中提取位同步信号，这种直接法按其提取同步信号的方式，大致可分为滤波法和锁相法。锁相法是指利用锁相环来提取位同步信号的方法，本设计方案就是基于锁相环的位同步提取方法，能够比较快速地提取位同步时钟，并且设计简单，方便修改参数。采用Quartus II设计软件对系统进行了仿真试验，并用Altera的Cyclone II系列FPGA芯片Ep2c5予以实现。(In digital communication, usually from receiving directly in digital signal extracted a synchronized signal, the direct method according to the extraction synchronized signal way, can be roughly divided into filtering method and phase lock method. Phase lock method is using of phase locked loop to extract a synchronized signal method, the design scheme is based on phase locked loop of a synchronous extraction method and can be quickly extract a synchronous clock, and design simple, convenient modification parameter. The Quartus II design software of the system, and the simulation test Altera Cyclone II FPGA chip to achieve Ep2c5 series.)
- 2020-12-01 10:39:28下载
- 积分：1
-
spi
该程序是一个可完成订制化的SPI双向总线接口，时钟相位、极性，以及分频比全部可通过寄存器进行配置，已经在ISE下通过综合，占用资源少，强烈推荐
(The program is a complete custom of SPI bidirectional bus interface, clock phase, polarity, and the divider ratio can all be configured through the register, has been in the ISE through an integrated, small footprint, it is strongly recommended)
- 2013-07-02 14:07:16下载
- 积分：1
-
VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题
VHDL开发的计数器。源程序不复杂，应该都能看懂。最重要的注意：是时序问题-VHDL development of the counter. Source code is not complicated, should be able to understand. The most important Note : Timing is the issue
- 2022-05-14 00:07:18下载
- 积分：1
-
跑马灯程序FPGA
FPGA跑马灯程序,基于CPLD1270开发板的运用程序-Marquee program FPGA-based development board CPLD1270 the use of procedures
- 2022-02-04 16:36:32下载
- 积分：1
-
用于sopc builder添加组件用的ps/2
键盘 ipcore
用于sopc builder添加组件用的ps/2
键盘 ipcore-Sopc builder used to add components used ps/2 keyboard IPCore
- 2022-03-12 14:54:04下载
- 积分：1
