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JESD204B_character
JESD204协议简单透彻的讲解，对做高速AD的朋友有一定的帮助(Understanding control characters in JESD204)
- 2014-10-11 16:17:23下载
- 积分：1
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OFDM_CP
ofdm系统的matlab实现，包括插入导频信号和循环前缀(Matlab implementation of ofdm system, including inserted pilot frequency signal and the cyclic prefix)
- 2013-05-29 10:10:23下载
- 积分：1
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FSK信号发生器，基于VHDL语言，好用的！
FSK信号发生器，基于VHDL语言，好用的！-FSK signal generator, based on the VHDL language, useful!
- 2022-06-19 14:00:10下载
- 积分：1
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IIC主设备的代码实现（verilog),从设备模型
IIC主设备的代码实现（verilog),从设备模型-IIC main equipment of the code (verilog), from the device model
- 2022-09-07 15:50:02下载
- 积分：1
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ANALYSIS-OF-FULL-ADDER
DESCRIPTION OF FULL ADDER
- 2013-11-12 13:32:19下载
- 积分：1
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VHDL子程序集,包括各种例程资料以及源码.
VHDL子程序集,包括各种例程资料以及源码.-VHDL subprogram, including a variety of routine information as well as the source.
- 2022-07-01 03:40:13下载
- 积分：1
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海力士公司8M字节的SDR SDRAM实现Verilog仿真语言。
Hynix公司8M byte sdr sdram的verilog语言仿真实现。-Hynix company 8M byte sdr sdram realize the Verilog simulation language.
- 2023-07-14 06:05:04下载
- 积分：1
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DCM_SP
数字时钟管理器，xilinx公司开发板集成时钟，实现分频、倍频等功能。(Digital clock managers, xilinx development board integrated clock divider, multiplier, and other functions.)
- 2021-02-19 09:59:44下载
- 积分：1
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task_function
自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过(I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through)
- 2008-06-26 21:21:23下载
- 积分：1
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half_band
半带滤波器verilog源代码，主要用于采样率变换系统中，采用乘法积累加器，很好的例子，供大家参考(Half band filter verilog code, mainly for the sampling rate conversion system, use the multiplication accumulation adder, a good example, for your reference)
- 2020-12-23 10:59:07下载
- 积分：1
