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ad706_verilog
AD706在Sparten6使用的FPGA代码，测试通过(AD706 FPGA Code In Sparten6)
- 2017-02-06 10:39:29下载
- 积分：1
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SMBUS总线的verilog实现
实现两个状态机和不同的数据传输方式，按照smbus总线的要求进行调节每位的传输，从起始位到终值位，能够较好的实现
- 2022-03-25 14:06:09下载
- 积分：1
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VHDL-development
VHDL入门级好教材《VHDL开发精解与实例剖析》(VHDL development solution with fine examples of analysis)
- 2015-03-11 10:57:53下载
- 积分：1
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AHB_slave ram
ram 的ahb接口，ram ahb interface 好用的中转接口ram 的ahb(ram ahb interface
ram ahb interface ram ahb interface)
- 2021-04-20 17:38:50下载
- 积分：1
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uart_tx
FPGA UART 发送端程序 verilog语言编写
9600波特率 实用(UART transmit side program verilog language 9600 baud)
- 2013-08-14 16:33:34下载
- 积分：1
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PID controller verilog源代码
The PID controller IP core performs digital proportional–integral–derivative controller (PID controller) algorithm. The algorithm first calculates the error between a measured value (PV) and its ideal value (SP), then use the error as an argument to calculate the manipulate value(MV). The MV will adjust the process to minimize the error. It can be used to calculate duty cycle for PWM (Pulse Width Modulation).
- 2022-09-23 12:05:03下载
- 积分：1
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fwPVerlilog
68013与FPGA的通信，包含了固件程序与verilog程序(68013 and FPGA communication, including firmware and verilog program)
- 2013-06-19 16:04:40下载
- 积分：1
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total
一个简单的后台模板，主要为贵金属直播室有喊单等功能类型的。
ps：由于涉及到iframe本地跨域问题，因此查看时请在服务器上进行审阅。(A simple background template, mainly for the precious metal living room, such as the type of function.
PS: as a result of the local cross domain problem involved in the iframe, so check it out on the server.)
- 2015-11-18 09:00:49下载
- 积分：1
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Decoder_CC_P
Convolotional Decoding Based on Viterbi Algorithm
- 2021-05-13 16:30:02下载
- 积分：1
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xilinx-FPGA
xilinx FPGA技术详解,从设计流程到设计注意点(xilinx FPGA technology Detailed Design points, from the design process to)
- 2012-08-10 13:07:41下载
- 积分：1
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