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clock
软件开发环境:ISE 7.1i 仿真环境:ModelSim SE 6.0 1. 多功能数字钟(Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.0 1. Multi-function digital clock)
- 2009-03-22 12:44:34下载
- 积分:1
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归档
ddr3使用教学(DDR3 using teaching)
- 2018-03-19 09:57:19下载
- 积分:1
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IIC EEPROM verilog 代码
EEPROM HDC2010温湿度传感器的verilog读写代码,IIC通信,Verilog,测试通过
- 2023-02-28 20:45:03下载
- 积分:1
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bingchuan
说明: 简单的vhdl的四位并串转换程序,可以实现数据的并串转换(Simple vhdl string of four and the conversion process, can convert the data and the string)
- 2011-04-02 12:16:35下载
- 积分:1
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FIFO
fifi asyncronous and syncronus
- 2012-04-30 02:31:24下载
- 积分:1
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rams
说明: combinatorial modules
- 2019-04-13 19:41:21下载
- 积分:1
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vga_demo2
VGA controller : Genarate a VGA signal from your inout information as color info of each pixel
- 2010-06-24 09:26:57下载
- 积分:1
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VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟,计数器进行加计数,并利用数码管进行显示,当计数到9999 时,从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分:1
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DDR2_16bit
说明: ddr2原理图设计,原厂电路图设计,很好很强大 16bit(ddr2 schematic design, the original schematic design, a very powerful 16bit)
- 2011-02-24 11:07:35下载
- 积分:1
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Exercise4
AES TSAPI Retrieve Event in Non-blocking Mode
- 2019-05-07 20:04:58下载
- 积分:1