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gtx_aurora_zc706_example
Aurora 8B/10B协议是Xilinx公司针对高速传输开发的一种可裁剪的轻量级链路层协议，通过一条或多条串行链路实现两设备间的数据传输。协议Aurora协议可以支持流和帧两种数据传输模式，以及全双工、单工等数据通信方式。(The Aurora 8B / 10B protocol is a tailor-made lightweight link layer protocol developed by Xilinx for high-speed transmission that enables data transfer between two devices over one or more serial links. Protocol Aurora protocol can support two data transfer modes, stream and frame, as well as full-duplex, simplex and other data communications.)
- 2018-01-23 08:53:37下载
- 积分：1
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szdyb
关于数字电压表的vhdl实现，有仿真程序，可以下载到板子中。(Vhdl digital voltage meter on the implementation of a simulation program can be downloaded to the board.)
- 2011-05-09 21:09:07下载
- 积分：1
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Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考....
Clock_Dithering_Verilog this is a Clock u_dither, 大家想要做Verilog去抖动的可以参考.-Clock_Dithering_Verilog this is a Clock u_dither, everybody want to make Verilog-jitter can refer to.
- 2022-12-08 19:40:03下载
- 积分：1
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I2C
I2C的实现，可以扩展进而控制有关I2C的器件达到操作员的控制目的。(I2C implementations, can be extended further having control of the I2C device operator control purposes.)
- 2015-06-06 21:21:05下载
- 积分：1
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一个多路复用器的例子，用VHDL语言写的。
A Mux example written in VHDL.
- 2023-01-13 15:05:04下载
- 积分：1
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Based on the VHDL language for selecting the three sequences, you can have a cyc...
基于VHDL语言的3级序列的产生，可以循环产生周期为7的m序列
-Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence
- 2023-08-16 17:00:04下载
- 积分：1
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24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。...
24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
- 2022-03-23 02:16:08下载
- 积分：1
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Verilog-shift-mulfunction
FPGA verilog 实现任意位宽的移位相乘法，有符号小数或者有符号整数相乘。函数调用方式(FPGA verilog achieve any bit-wide shift multiplication , signed or signed decimal integer multiplication . Function call
)
- 2014-06-21 17:08:12下载
- 积分：1
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taxi
利用Verilog HDL语言设计了出租车计费器，使其具有时间 显示、计费以及模拟出租车启动、停止、复位等功能，并设置了动态扫描电路显示车费和对应时间，显示 了硬件描述语言Verilog—HDL设计数字逻辑电路的优越性。(Design using Verilog HDL language a taxi meter, it has time display, billing and simulation taxi start, stop, reset and other functions, and set dynamically display scanning circuit and the corresponding time fare, shows the hardware description language Verilog-HDL design advantages of digital logic circuits.)
- 2011-08-30 08:18:51下载
- 积分：1
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1553B总线接口技术研究及FPGA实现
基于FPGA的1553b接口设计详细设计论文(1553B design based on FPGA)
- 2019-04-18 11:02:52下载
- 积分：1
