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cnt60
六十进制计数器,VHDL编写的计数器,本科电子的可能有些实验可以用到(counter Possible experiments of undergraduate electronics can be used)
- 2021-04-07 11:59:01下载
- 积分:1
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SPITX16
基于状态机的优秀SPI输出程序(以DAC7512为基础,可修改)(VHDL code about SPI)
- 2016-02-09 01:07:52下载
- 积分:1
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LED-clock-display
利用单片机控制LED时钟显示,以及闹钟,程序较大,但比较简单易懂。(LED clock display)
- 2013-03-10 10:15:37下载
- 积分:1
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aurora_IP
Aurora协议是一款高带宽、低成本、可扩展、框架简洁、适合点对点串行数据传输的协议。(Aurora protocol is a high-bandwidth, low-cost, scalable, simple framework for point to point serial data transfer protocol.)
- 2017-03-10 17:16:22下载
- 积分:1
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add_noisem
把指定的噪声叠加到信号上去.有标准噪声库NOISEX-92,其中带有白噪声、办公室噪声、工厂噪声、汽车噪声、坦克噪声等等,在信号处理中往往需要把库中的噪声叠加到信号中去,而噪声的采样频率与纯信号的采样频率往往不一致,需要采样频率的校准。
(The specified noise superimposed to the signal up. Standard noise library NOISEX-92, with white noise, office noise, factory noise, car noise, tank noise in the signal processing often requires noise to be superimposed in the library The signal to noise of the sampling frequency and pure signal sampling frequency is often inconsistent sampling frequency of calibration.)
- 2012-08-10 14:18:33下载
- 积分:1
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xilinx读取DEVICE DNA源码
网上有类似的源码(dna_rd.v)但是有错误,里面第133行起,有两句没有放在begin end 里面,原本执行s6的状态机是有选择的进入s5或s7,而遗漏begin end 是直接进入s7,因此执行错误,dna读取全为0
- 2022-10-06 07:35:03下载
- 积分:1
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16位二进制转化为BCD码
此代码可以实现16位二进制和BCD码之间的转换。(This code can realize the conversion between 16 bit binary and BCD code.)
- 2018-10-31 13:31:13下载
- 积分:1
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mancheshitebianjiema
用VHDL编写的曼切斯特编解码,适用于以太网上流行的基带传输数字编码。(Manchester encoding and decoding written using VHDL, popular Ethernet baseband transmission of digital coding.)
- 2012-05-25 15:16:35下载
- 积分:1
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shuzi
讲述了全数字信号发生器部分频率值测算的表格(Full digital signal generator frequency value calculation form
)
- 2011-12-17 00:55:01下载
- 积分:1
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1024-point-FFT-in-verilog.pdf
1024 点得快速傅里叶变换算法 FPGA in verilog(1024 point FFT on a FPGA written in verilog)
- 2014-03-26 22:56:23下载
- 积分:1