登录
首页 » Verilog » FPGA 的数字闹钟

FPGA 的数字闹钟

于 2022-03-10 发布 文件大小:1,022.70 kB
0 103
下载积分: 2 下载次数: 1

代码说明:

这个项目旨在在 FPGA 上实现数字闹钟的功能。尽快 FPGA 打开时,时钟就开始了。可以使用 FPGA 板上提供 dip 开关设置报警。通过相应的 dip 开关指示灯表明了这一点。计数器保持工作,一旦报警消除,像声音放大通过扬声器蜂鸣器。 该项目是充分的。享受它吧 !

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • lesson1
    eda的入门学习课件,老师不错,内容页挺好的(eda learning files)
    2012-12-14 22:39:31下载
    积分:1
  • sopc
    基于FPGA的SD卡音频播放器 经过调试可以直接用,音质很好有MP3的所有功能(FPGA-based audio player, SD card can be directly used after debugging, good sound quality with all the features of MP3)
    2021-01-02 23:08:57下载
    积分:1
  • halfband
    verilog写的39阶通带为20KHz的半带fir滤波器,经测试正确。(verilog halfband FIR)
    2020-12-25 14:29:04下载
    积分:1
  • zhinengchezaishipingxitong
    设计了车载视频显示系统,设计了基于FPGA系统结构的车载视频显示电路板,利用FPGA显示视频控制,采集通道时许控制等。(The on-board video display system design, design the system structure based on FPGA video shows the circuit board, using the FPGA show video control, acquisition channel make control, etc )
    2011-12-08 15:37:21下载
    积分:1
  • gobang
    一个用verilog实现的五子棋程序,用在fpga上,连接显示器,可选择与电脑对战或是双人对战,按wsad控制方向,回车控制落子,程序会自动判断输赢并显示结果(A 331 procedures implemented by verilog, used in fpga, connect the monitor, you can choose to play against the computer or a double play, press wsad control the direction, carriage control Lazi, the program will automatically determine the winners and losers and display the results)
    2015-03-30 13:13:35下载
    积分:1
  • cpu110
    基本功能的cpu,自定义内存内容~了解CPU运作原理~(design of cpu,VHDL environment~)
    2016-04-25 10:13:26下载
    积分:1
  • FPGA I2C IP
    应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used to set the register address pointer, and write the register data. I2C reads are used to read the register data. Successive data reads or writes result in data being read or written from incremental register addresses. There is no limit on how much data can be read or written in a single access, but the internal register address pointer will wrap round to 0 once it reaches 255. Note that the address pointer is not initialized at reset, and the address pointer must
    2022-05-22 00:28:39下载
    积分:1
  • commutator
    使用FPGA实现三相直流无刷电机换相,该程序可以使用(Use FPGA to realize the three-phase brushless DC motor commutation, the program can use)
    2014-05-26 22:34:32下载
    积分:1
  • ARMPFPGA-JTAG
    ARM+FPGA JTAG(二合一)原理图与PCB(ARM+ FPGA JTAG (combined) schematic and PCB )
    2014-07-28 21:28:03下载
    积分:1
  • class-test
    自己编写的C++的类的测试程序,有详细的注注释,对初学者有很大帮助!!!(The own written C++ class test program, detailed annotation of Note of great help for beginners! ! !)
    2012-08-28 09:24:41下载
    积分:1
  • 696518资源总数
  • 106222会员总数
  • 14今日下载