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800 x 600 60 Hz VGA 控制器 FLEX10

于 2023-08-31 发布文件大小:2.20 MB

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800 x 600 60 hz VGA 控制器。简单的 verilog 代码。软件项目包括。

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67_ellipf
vhdl very good debug release vhdl very good debug release

2006-10-22 18:39:48下载

积分：1
基于sopc的IIC总线设计完整设计sopcIIC
该例子是基于sopc的IIC总线设计完整设计，分为硬件和软件部分，软件部分是用c语言编写的。该项目是个以完成的项目，据有较高的参考和经济价值。该例子是原来做过的项目。整个项目是在Quartus II 7.0和nios IDE环境下开发。 (This example is based on the IIC bus design sopc complete design, divided into hardware and software, the software part is written in c language. The project is to complete the project, according to the reference and a higher economic value. The example is a project originally done. The whole project is in the Quartus II 7.0 and the nios IDE development environment.)

2020-07-12 00:58:53下载

积分：1
Chapter11-13
第十一章到第十三章的代码本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。(Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.)

2009-11-17 13:57:09下载

积分：1
基于VGA显示的10路逻辑分析仪
FPGA 的VGA显示应用。最大采样频率100M，共十个采样通道，存储深度为每通道1024位。带时间标线，显示区域可移动。最终将波形数据显示到VGA显示器上。用Quartus ii进行设计，仿真工作。最后可在开发板上进行硬件测试。

2023-04-08 01:00:04下载

积分：1
fulladd
this files in Quartus2 are fulladder

2016-05-17 16:38:42下载

积分：1
e_BIU
说明： isa MEMORY PLAN eu biu asm

2020-06-25 19:20:02下载

积分：1
apb_uart
这里是apb总线设计代码。这个源程序是基于verilog语言设计的(Here is the APB bus design code. This source program is designed based on Verilog language)

2021-04-12 14:18:57下载

积分：1
AHB_SMSS
ahb single master single slave rtl design

2021-04-21 11:28:49下载

积分：1
52_divider
多倍（次）分频器请注意: 本例的各个源描述的编译顺序应该是: 52_divider.vhd 52_divider_stim.vhd (Times (times) divider Please note: This case is described in various sources to compile the order should be: 52_divider.vhd 52_divider_stim.vhd)

2009-09-04 09:52:18下载

积分：1
5956474temperature
DS18b20 temperature sensor vhdl code

2010-07-04 03:46:44下载

积分：1

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800 x 600 60 Hz VGA 控制器 FLEX10

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