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主要介绍了ＦＰＧＡ设计的基本原则、基本设计思想、基本操作技巧、常用模块。...
主要介绍了ＦＰＧＡ设计的基本原则、基本设计思想、基本操作技巧、常用模块。-Mainly introduces the basic principles of FPGA design, basic design concepts, basic operating skills, commonly used modules.
- 2022-08-25 13:03:15下载
- 积分：1
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Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0],...
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
- 2022-04-13 06:40:15下载
- 积分：1
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adda
说明： 基于FPGA 黑金ALINX 515的 ADDA采样模块源码（需调试）(ADDA Sampling Module Source Code Based on FPGA Heijin ALINX 515)
- 2020-06-20 13:00:01下载
- 积分：1
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vhdl实现的鼠标协议，代码可读性高，适合作为参考案例。
vhdl实现的鼠标协议，代码可读性高，适合作为参考案例。-VHDL realize mouse agreement, the code readable, suitable as a reference case.
- 2022-02-06 08:18:06下载
- 积分：1
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AXI-full
axi协议中的full子协议，可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
- 2018-03-15 10:40:55下载
- 积分：1
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I2C interface standard modeling source
I2C接口标准建模源码,I2C interface standard modeling source-I2C interface standard modeling source
- 2022-01-24 12:53:13下载
- 积分：1
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ISARCSSim_dr
基于CS的一维距离像（HRRP）及FFT成像对比(CS-based HRRP and FFT HRRP)
- 2021-01-13 19:58:49下载
- 积分：1
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FIFO
Verilog HDL语言编写异步FIFO(Verilog HDL language, asynchronous FIFO)
- 2012-05-31 15:13:21下载
- 积分：1
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mutiplier
说明： 用VHDL语言仿真乘法器设计, 经过modelsim仿真， synplify综合，并下载进FPGA验证(Multiplier design using VHDL, simulation, after modelsim simulation, synplify synthesis, and downloaded into a FPGA verification)
- 2009-08-28 13:28:04下载
- 积分：1
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LED blinker : LED1 blink every second, LED2 blink every minute
与Xilinx spartan6评估委员会结合的小型项目示例。
- 2023-02-03 21:50:03下载
- 积分：1
