NTR2120
超低速的光纤一体发接收发送器,同于以前的光纤一体化接头都只适用于2M以上的通讯,如需将232等低速信号用光纤传输出,需要加复杂的调制解调电路,网动光电新生产的这款光纤头主要针对低速信号,可以传送DC-500KPS的信号,极大地简化了硬件设计.(Ultra-low-fat whole-speed fiber-optic transmitter receiver with fiber-optic integration in the previous joint only applies to more than 2M communications, etc. For the 232 low-speed optical fiber transmission of signals, the need to increase the complexity of the modulation and demodulation circuit, the net move Photoelectric new production of this first major response to low-speed fiber-optic signal, DC-500KPS can send the signal, greatly simplifying the hardware design.)
- 2008-06-27 11:48:58下载
- 积分：1
udp_send1
基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data_valid,
input gtx_clk,
output logic tx_en(UDP hardware stack, written in system verilog, do nt need CPU.Projgect includes MAC Layer,support phy configuration.support gmii and rgmii mode. the interface is as the follows:
input clk50,
input rst_n,
///////////////////////
//interface to user module
input [7:0] wr_data,
input wr_clk,
input wr_en,
output wr_full,
output [7:0] rd_data,
input rd_clk,
input rd_en,
output rd_empty,
input [31:0] local_ipaddr, //FPGA ip address
input [31:0] remote_ipaddr, //PC ip address
input [15:0] local_port, //FPGA port number
//interface to ethernet phy
output mdc,
inout mdio,
output phy_rst_n,
output is_link_up,
`ifdef RGMII_IF
input [3:0] rx_data,
output logic [3:0] tx_data,
`else
input [7:0] rx_data,
output logic [7:0] tx_data,
`endif
input rx_clk,
input rx_data)
- 2016-03-10 15:23:29下载
- 积分：1
