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一个完整的viterbi译码程序和测试的程序
一个完整的viterbi译码程序和测试的程序-A complete viterbi decoding procedures and test procedures
- 2023-01-14 14:40:03下载
- 积分：1
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FIFO
Simulation and Synthesis Techniques for Asynchronous
FIFO Design
- 2013-08-27 16:07:08下载
- 积分：1
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multiply_8_VHDL
由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方
法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。(an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and a top level design document.)
- 2014-04-11 16:58:04下载
- 积分：1
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ise
xilinx的时序约束实验，通过阅读本文档，你可以用全局时序约束来轻松提高已有的项目的系统时钟频率，同时你还可以用映射后静态时序报告以及布局布线后静态时序报告来分析你的设计性能(Xilinx timing constraints of the experiment, by reading this document, you can use the overall timing constraints to easily enhance existing projects the system clock frequency, at the same time you can also use static timing report after mapping, as well as after placement and routing static timing analysis report to you design performance)
- 2007-09-20 14:30:52下载
- 积分：1
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i2c_master_top
i2c core : i2c master top
- 2012-05-23 01:17:22下载
- 积分：1
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canny
说明： canny 边缘检测基于梯度直方图的自适应阈值verilog实现(Canny edge detection based on gradient histogram adaptive threshold Verilog implementation)
- 2021-04-12 14:48:57下载
- 积分：1
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在ise10.1.3 Xilinx PicoBlaze的应用开发。
Xilinx PicoBlaze application developed in ISE10.1.3.
- 2023-07-28 07:25:03下载
- 积分：1
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dac
简易函数发生器，能产生正弦波，三角波，梯形波，方波，并且可调频率和幅度值。(Simple function generator can produce sine, triangle wave, trapezoidal wave, square wave, and the adjustable frequency and amplitude values.)
- 2011-08-28 14:11:37下载
- 积分：1
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hammingaTB
Design HDL code for a circuit that calculates the Hamming distance of two 8-bit inputs.
- 2013-11-06 15:45:02下载
- 积分：1
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利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的
利用Verilog HDL对AD7705进行控制ADC采样，实验室师兄的-Using Verilog HDL to the AD7705 control ADC sampling, laboratory师兄the
- 2023-01-10 03:55:04下载
- 积分：1
